2 * Command line: opannotate --source
4 * Interpretation of command line:
5 * Output annotated source file with samples
8 * CPU: Core 2, speed 2133.49 MHz (estimated)
9 * Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a unit mask of 0x00
10 * (Unhalted core cycles) count 100000
13 * Total samples for file : "/home/cworth/src/xorg/driver/xf86-video-intel/src/i965_render.c"
19 :i965_prepare_composite(int op, PicturePtr pSrcPicture,
20 : PicturePtr pMaskPicture, PicturePtr pDstPicture,
21 : PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
22 304 0.0108 :{ /* i965_prepare_composite total: 830728 29.6474 */
23 1017 0.0363 : ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
24 184 0.0066 : I830Ptr pI830 = I830PTR(pScrn);
25 : CARD32 src_offset, src_pitch;
26 : CARD32 mask_offset = 0, mask_pitch = 0;
27 : CARD32 dst_format, dst_offset, dst_pitch;
28 : Bool rotation_program = FALSE;
30 22 7.9e-04 : IntelEmitInvarientState(pScrn);
31 103 0.0037 : *pI830->last_3d = LAST_3D_RENDER;
33 153 0.0055 : src_offset = intel_get_pixmap_offset(pSrc);
34 65 0.0023 : src_pitch = intel_get_pixmap_pitch(pSrc);
35 160 0.0057 : dst_offset = intel_get_pixmap_offset(pDst);
36 72 0.0026 : dst_pitch = intel_get_pixmap_pitch(pDst);
37 25 8.9e-04 : if (pMask) {
38 27 9.6e-04 : mask_offset = intel_get_pixmap_offset(pMask);
39 28 1.0e-03 : mask_pitch = intel_get_pixmap_pitch(pMask);
41 245 0.0087 : pI830->scale_units[0][0] = pSrc->drawable.width;
42 54 0.0019 : pI830->scale_units[0][1] = pSrc->drawable.height;
44 64 0.0023 : pI830->transform[0] = pSrcPicture->transform;
47 6 2.1e-04 : pI830->transform[1] = NULL;
48 56 0.0020 : pI830->scale_units[1][0] = -1;
49 2 7.1e-05 : pI830->scale_units[1][1] = -1;
50 16 5.7e-04 : if (pI830->transform[0] &&
51 : i965_check_rotation_transform(pI830->transform[0]))
52 : rotation_program = TRUE;
54 44 0.0016 : pI830->transform[1] = pMaskPicture->transform;
55 125 0.0045 : pI830->scale_units[1][0] = pMask->drawable.width;
56 99 0.0035 : pI830->scale_units[1][1] = pMask->drawable.height;
59 : /* setup 3d pipeline state */
61 30 0.0011 : binding_table_entries = 2; /* default no mask */
63 : /* Wait for sync before we start setting up our new state */
65 : i830WaitSync(pScrn);
68 : /* Set up our layout of state in framebuffer. First the general state: */
70 31 0.0011 : vs_offset = ALIGN(next_offset, 64);
71 : next_offset = vs_offset + sizeof(*vs_state);
73 5 1.8e-04 : sf_offset = ALIGN(next_offset, 32);
74 : next_offset = sf_offset + sizeof(*sf_state);
76 14 5.0e-04 : wm_offset = ALIGN(next_offset, 32);
77 : next_offset = wm_offset + sizeof(*wm_state);
79 25 8.9e-04 : wm_scratch_offset = ALIGN(next_offset, 1024);
80 : next_offset = wm_scratch_offset + 1024 * PS_MAX_THREADS;
82 31 0.0011 : cc_offset = ALIGN(next_offset, 32);
83 : next_offset = cc_offset + sizeof(*cc_state);
85 : /* keep current sf_kernel, which will send one setup urb entry to
88 6 2.1e-04 : sf_kernel_offset = ALIGN(next_offset, 64);
90 14 5.0e-04 : next_offset = sf_kernel_offset + sizeof (sf_kernel_static_mask);
91 : else if (rotation_program)
92 : next_offset = sf_kernel_offset + sizeof (sf_kernel_static_rotation);
94 : next_offset = sf_kernel_offset + sizeof (sf_kernel_static);
96 34 0.0012 : ps_kernel_offset = ALIGN(next_offset, 64);
98 : if (pMaskPicture->componentAlpha &&
99 : PICT_FORMAT_RGB(pMaskPicture->format)) {
100 : if (i965_blend_op[op].src_alpha) {
101 : next_offset = ps_kernel_offset +
102 : sizeof(ps_kernel_static_maskca_srcalpha);
104 : next_offset = ps_kernel_offset +
105 : sizeof(ps_kernel_static_maskca);
108 114 0.0041 : next_offset = ps_kernel_offset +
109 : sizeof(ps_kernel_static_masknoca);
110 : } else if (rotation_program) {
111 : next_offset = ps_kernel_offset + sizeof (ps_kernel_static_rotation);
113 99 0.0035 : next_offset = ps_kernel_offset + sizeof (ps_kernel_static_nomask);
116 198 0.0071 : sip_kernel_offset = ALIGN(next_offset, 64);
117 : next_offset = sip_kernel_offset + sizeof (sip_kernel_static);
120 97 0.0035 : cc_viewport_offset = ALIGN(next_offset, 32);
121 : next_offset = cc_viewport_offset + sizeof(*cc_viewport);
123 : /* for texture sampler */
124 72 0.0026 : src_sampler_offset = ALIGN(next_offset, 32);
125 30 0.0011 : next_offset = src_sampler_offset + sizeof(*src_sampler_state);
127 112 0.0040 : if (pMask) {
128 14 5.0e-04 : mask_sampler_offset = ALIGN(next_offset, 32);
129 31 0.0011 : next_offset = mask_sampler_offset + sizeof(*mask_sampler_state);
131 : /* Align VB to native size of elements, for safety */
132 337 0.0120 : vb_offset = ALIGN(next_offset, 8);
133 : next_offset = vb_offset + vb_size;
135 : /* And then the general state: */
136 184 0.0066 : dest_surf_offset = ALIGN(next_offset, 32);
137 : next_offset = dest_surf_offset + sizeof(*dest_surf_state);
139 136 0.0049 : src_surf_offset = ALIGN(next_offset, 32);
140 390 0.0139 : next_offset = src_surf_offset + sizeof(*src_surf_state);
142 55 0.0020 : if (pMask) {
143 28 1.0e-03 : mask_surf_offset = ALIGN(next_offset, 32);
144 28 1.0e-03 : next_offset = mask_surf_offset + sizeof(*mask_surf_state);
145 9 3.2e-04 : binding_table_entries = 3;
148 84 0.0030 : binding_table_offset = ALIGN(next_offset, 32);
149 : next_offset = binding_table_offset + (binding_table_entries * 4);
151 155 0.0055 : default_color_offset = ALIGN(next_offset, 32);
152 43 0.0015 : next_offset = default_color_offset + sizeof(*default_color_state);
154 36 0.0013 : total_state_size = next_offset;
155 : assert(total_state_size < pI830->exa_965_state->size);
157 103 0.0037 : state_base_offset = pI830->exa_965_state->offset;
158 84 0.0030 : state_base_offset = ALIGN(state_base_offset, 64);
159 173 0.0062 : state_base = (char *)(pI830->FbBase + state_base_offset);
161 12 4.3e-04 : vs_state = (void *)(state_base + vs_offset);
162 36 0.0013 : sf_state = (void *)(state_base + sf_offset);
163 43 0.0015 : wm_state = (void *)(state_base + wm_offset);
164 38 0.0014 : cc_state = (void *)(state_base + cc_offset);
165 29 0.0010 : sf_kernel = (void *)(state_base + sf_kernel_offset);
166 79 0.0028 : ps_kernel = (void *)(state_base + ps_kernel_offset);
167 31 0.0011 : sip_kernel = (void *)(state_base + sip_kernel_offset);
169 63 0.0022 : cc_viewport = (void *)(state_base + cc_viewport_offset);
171 25 8.9e-04 : dest_surf_state = (void *)(state_base + dest_surf_offset);
172 64 0.0023 : src_surf_state = (void *)(state_base + src_surf_offset);
173 37 0.0013 : if (pMask)
174 17 6.1e-04 : mask_surf_state = (void *)(state_base + mask_surf_offset);
176 104 0.0037 : src_sampler_state = (void *)(state_base + src_sampler_offset);
178 20 7.1e-04 : mask_sampler_state = (void *)(state_base + mask_sampler_offset);
180 55 0.0020 : binding_table = (void *)(state_base + binding_table_offset);
182 42 0.0015 : vb = (void *)(state_base + vb_offset);
184 65 0.0023 : default_color_state = (void*)(state_base + default_color_offset);
186 : /* Set up a default static partitioning of the URB, which is supposed to
187 : * allow anything we would want to do, at potentially lower performance.
189 :#define URB_CS_ENTRY_SIZE 0
190 :#define URB_CS_ENTRIES 0
192 :#define URB_VS_ENTRY_SIZE 1 // each 512-bit row
193 :#define URB_VS_ENTRIES 8 // we needs at least 8 entries
195 :#define URB_GS_ENTRY_SIZE 0
196 :#define URB_GS_ENTRIES 0
198 :#define URB_CLIP_ENTRY_SIZE 0
199 :#define URB_CLIP_ENTRIES 0
201 :#define URB_SF_ENTRY_SIZE 2
202 :#define URB_SF_ENTRIES 1
204 25 8.9e-04 : urb_vs_start = 0;
205 21 7.5e-04 : urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
206 40 0.0014 : urb_gs_start = urb_vs_start + urb_vs_size;
207 58 0.0021 : urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
208 58 0.0021 : urb_clip_start = urb_gs_start + urb_gs_size;
209 50 0.0018 : urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
210 46 0.0016 : urb_sf_start = urb_clip_start + urb_clip_size;
211 52 0.0019 : urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
212 42 0.0015 : urb_cs_start = urb_sf_start + urb_sf_size;
213 43 0.0015 : urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
215 : /* Because we only have a single static buffer for our state currently,
216 : * we have to sync before updating it every time.
219 : i830WaitSync(pScrn);
222 274 0.0098 : memset (cc_viewport, 0, sizeof (*cc_viewport));
223 124 0.0044 : cc_viewport->min_depth = -1.e35;
224 122 0.0044 : cc_viewport->max_depth = 1.e35;
226 : /* Color calculator state */
227 861 0.0307 : memset(cc_state, 0, sizeof(*cc_state));
228 18559 0.6623 : cc_state->cc0.stencil_enable = 0; /* disable stencil */
229 17836 0.6365 : cc_state->cc2.depth_test = 0; /* disable depth test */
230 12306 0.4392 : cc_state->cc2.logicop_enable = 0; /* disable logic op */
231 : cc_state->cc3.ia_blend_enable = 1; /* blend alpha just like colors */
232 7308 0.2608 : cc_state->cc3.blend_enable = 1; /* enable color blend */
233 10 3.6e-04 : cc_state->cc3.alpha_test = 0; /* disable alpha test */
234 9645 0.3442 : cc_state->cc4.cc_viewport_state_offset = (state_base_offset +
235 : cc_viewport_offset) >> 5;
236 7354 0.2625 : cc_state->cc5.dither_enable = 0; /* disable dither */
237 926 0.0330 : cc_state->cc5.logicop_func = 0xc; /* COPY */
238 2780 0.0992 : cc_state->cc5.statistics_enable = 1;
239 63 0.0022 : cc_state->cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD;
240 32 0.0011 : i965_get_blend_cntl(op, pMaskPicture, pDstPicture->format,
241 : &src_blend, &dst_blend);
242 : /* XXX: alpha blend factor should be same as color, but check
243 : * for CA case in future
245 14089 0.5028 : cc_state->cc5.ia_src_blend_factor = src_blend;
246 301 0.0107 : cc_state->cc5.ia_dest_blend_factor = dst_blend;
247 13845 0.4941 : cc_state->cc6.blend_function = BRW_BLENDFUNCTION_ADD;
248 31 0.0011 : cc_state->cc6.src_blend_factor = src_blend;
249 2361 0.0843 : cc_state->cc6.dest_blend_factor = dst_blend;
250 : cc_state->cc6.clamp_post_alpha_blend = 1;
251 4466 0.1594 : cc_state->cc6.clamp_pre_alpha_blend = 1;
252 359 0.0128 : cc_state->cc6.clamp_range = 0; /* clamp range [0,1] */
254 : /* Upload system kernel */
255 86 0.0031 : memcpy (sip_kernel, sip_kernel_static, sizeof (sip_kernel_static));
257 : /* Set up the state buffer for the destination surface */
258 332 0.0118 : memset(dest_surf_state, 0, sizeof(*dest_surf_state));
259 15291 0.5457 : dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
260 67 0.0024 : dest_surf_state->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32;
261 39 0.0014 : i965_get_dest_format(pDstPicture, &dst_format);
262 14430 0.5150 : dest_surf_state->ss0.surface_format = dst_format;
264 : dest_surf_state->ss0.writedisable_alpha = 0;
265 361 0.0129 : dest_surf_state->ss0.writedisable_red = 0;
266 : dest_surf_state->ss0.writedisable_green = 0;
267 : dest_surf_state->ss0.writedisable_blue = 0;
268 14076 0.5024 : dest_surf_state->ss0.color_blend = 1;
269 : dest_surf_state->ss0.vert_line_stride = 0;
270 : dest_surf_state->ss0.vert_line_stride_ofs = 0;
271 : dest_surf_state->ss0.mipmap_layout_mode = 0;
272 : dest_surf_state->ss0.render_cache_read_mode = 0;
274 36 0.0013 : dest_surf_state->ss1.base_addr = dst_offset;
275 420 0.0150 : dest_surf_state->ss2.height = pDst->drawable.height - 1;
276 14567 0.5199 : dest_surf_state->ss2.width = pDst->drawable.width - 1;
277 : dest_surf_state->ss2.mip_count = 0;
278 398 0.0142 : dest_surf_state->ss2.render_target_rotation = 0;
279 11691 0.4172 : dest_surf_state->ss3.pitch = dst_pitch - 1;
281 : /* Set up the source surface state buffer */
282 66 0.0024 : memset(src_surf_state, 0, sizeof(*src_surf_state));
283 13897 0.4960 : src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
284 14657 0.5231 : src_surf_state->ss0.surface_format = i965_get_card_format(pSrcPicture);
286 : src_surf_state->ss0.writedisable_alpha = 0;
287 25 8.9e-04 : src_surf_state->ss0.writedisable_red = 0;
288 : src_surf_state->ss0.writedisable_green = 0;
289 : src_surf_state->ss0.writedisable_blue = 0;
290 14981 0.5346 : src_surf_state->ss0.color_blend = 1;
291 : src_surf_state->ss0.vert_line_stride = 0;
292 : src_surf_state->ss0.vert_line_stride_ofs = 0;
293 : src_surf_state->ss0.mipmap_layout_mode = 0;
294 1 3.6e-05 : src_surf_state->ss0.render_cache_read_mode = 0;
296 26 9.3e-04 : src_surf_state->ss1.base_addr = src_offset;
297 127 0.0045 : src_surf_state->ss2.width = pSrc->drawable.width - 1;
298 6454 0.2303 : src_surf_state->ss2.height = pSrc->drawable.height - 1;
299 : src_surf_state->ss2.mip_count = 0;
300 15025 0.5362 : src_surf_state->ss2.render_target_rotation = 0;
301 243 0.0087 : src_surf_state->ss3.pitch = src_pitch - 1;
303 : /* setup mask surface */
305 48 0.0017 : memset(mask_surf_state, 0, sizeof(*mask_surf_state));
306 7037 0.2511 : mask_surf_state->ss0.surface_type = BRW_SURFACE_2D;
307 7619 0.2719 : mask_surf_state->ss0.surface_format =
308 : i965_get_card_format(pMaskPicture);
310 : mask_surf_state->ss0.writedisable_alpha = 0;
311 25 8.9e-04 : mask_surf_state->ss0.writedisable_red = 0;
312 : mask_surf_state->ss0.writedisable_green = 0;
313 : mask_surf_state->ss0.writedisable_blue = 0;
314 7789 0.2780 : mask_surf_state->ss0.color_blend = 1;
315 : mask_surf_state->ss0.vert_line_stride = 0;
316 : mask_surf_state->ss0.vert_line_stride_ofs = 0;
317 : mask_surf_state->ss0.mipmap_layout_mode = 0;
318 : mask_surf_state->ss0.render_cache_read_mode = 0;
320 15 5.4e-04 : mask_surf_state->ss1.base_addr = mask_offset;
321 37 0.0013 : mask_surf_state->ss2.width = pMask->drawable.width - 1;
322 3281 0.1171 : mask_surf_state->ss2.height = pMask->drawable.height - 1;
323 : mask_surf_state->ss2.mip_count = 0;
324 7624 0.2721 : mask_surf_state->ss2.render_target_rotation = 0;
325 71 0.0025 : mask_surf_state->ss3.pitch = mask_pitch - 1;
328 : /* Set up a binding table for our surfaces. Only the PS will use it */
329 94 0.0034 : binding_table[0] = state_base_offset + dest_surf_offset;
330 29 0.0010 : binding_table[1] = state_base_offset + src_surf_offset;
332 2 7.1e-05 : binding_table[2] = state_base_offset + mask_surf_offset;
334 : /* PS kernel use this sampler */
335 111 0.0040 : memset(src_sampler_state, 0, sizeof(*src_sampler_state));
336 24 8.6e-04 : src_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
337 12445 0.4441 : switch(pSrcPicture->filter) {
338 : case PictFilterNearest:
339 30 0.0011 : src_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST;
340 14939 0.5332 : src_sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
342 : case PictFilterBilinear:
343 5 1.8e-04 : src_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
344 5 1.8e-04 : src_sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
347 : I830FALLBACK("Bad filter 0x%x\n", pSrcPicture->filter);
350 15145 0.5405 : memset(default_color_state, 0, sizeof(*default_color_state));
351 : default_color_state->color[0] = 0.0; /* R */
352 41 0.0015 : default_color_state->color[1] = 0.0; /* G */
353 : default_color_state->color[2] = 0.0; /* B */
354 : default_color_state->color[3] = 0.0; /* A */
356 69 0.0025 : src_sampler_state->ss0.default_color_mode = 0; /* GL mode */
358 6323 0.2257 : if (!pSrcPicture->repeat) {
359 88 0.0031 : src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
360 5650 0.2016 : src_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
361 4660 0.1663 : src_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
362 532 0.0190 : src_sampler_state->ss2.default_color_pointer =
363 : (state_base_offset + default_color_offset) >> 5;
365 33 0.0012 : src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP;
366 343 0.0122 : src_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP;
367 9699 0.3461 : src_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
369 8398 0.2997 : src_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
371 3 1.1e-04 : if (pMask) {
372 104 0.0037 : memset(mask_sampler_state, 0, sizeof(*mask_sampler_state));
373 5 1.8e-04 : mask_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
374 8123 0.2899 : switch(pMaskPicture->filter) {
375 : case PictFilterNearest:
376 22 7.9e-04 : mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST;
377 7801 0.2784 : mask_sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
379 : case PictFilterBilinear:
380 : mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
381 : mask_sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
384 : I830FALLBACK("Bad filter 0x%x\n", pMaskPicture->filter);
387 7750 0.2766 : if (!pMaskPicture->repeat) {
388 85 0.0030 : mask_sampler_state->ss1.r_wrap_mode =
389 : BRW_TEXCOORDMODE_CLAMP_BORDER;
390 7668 0.2737 : mask_sampler_state->ss1.s_wrap_mode =
391 : BRW_TEXCOORDMODE_CLAMP_BORDER;
392 6142 0.2192 : mask_sampler_state->ss1.t_wrap_mode =
393 : BRW_TEXCOORDMODE_CLAMP_BORDER;
394 31 0.0011 : mask_sampler_state->ss2.default_color_pointer =
395 : (state_base_offset + default_color_offset)>>5;
397 : mask_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP;
398 1 3.6e-05 : mask_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP;
399 4 1.4e-04 : mask_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
401 : mask_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
404 : /* Set up the vertex shader to be disabled (passthrough) */
405 619 0.0221 : memset(vs_state, 0, sizeof(*vs_state));
406 15697 0.5602 : vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
407 6724 0.2400 : vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
408 8547 0.3050 : vs_state->vs6.vs_enable = 0;
409 : vs_state->vs6.vert_cache_disable = 1;
411 : /* Set up the SF kernel to do coord interp: for each attribute,
412 : * calculate dA/dx and dA/dy. Hand these interpolation coefficients
413 : * back to SF which then hands pixels off to WM.
416 303 0.0108 : memcpy(sf_kernel, sf_kernel_static_mask, sizeof (sf_kernel_static));
417 13 4.6e-04 : else if (rotation_program)
418 : memcpy(sf_kernel, sf_kernel_static_rotation,
419 : sizeof (sf_kernel_static_rotation));
421 60 0.0021 : memcpy(sf_kernel, sf_kernel_static, sizeof (sf_kernel_static));
423 558 0.0199 : memset(sf_state, 0, sizeof(*sf_state));
424 27418 0.9785 : sf_state->thread0.kernel_start_pointer =
425 : (state_base_offset + sf_kernel_offset) >> 6;
426 14701 0.5247 : sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
427 16615 0.5930 : sf_state->sf1.single_program_flow = 1;
428 6135 0.2189 : sf_state->sf1.binding_table_entry_count = 0;
429 : sf_state->sf1.thread_priority = 0;
430 1449 0.0517 : sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
431 : sf_state->sf1.illegal_op_exception_enable = 1;
432 12439 0.4439 : sf_state->sf1.mask_stack_exception_enable = 1;
433 14092 0.5029 : sf_state->sf1.sw_exception_enable = 1;
434 31133 1.1111 : sf_state->thread2.per_thread_scratch_space = 0;
435 : /* scratch space is not used in our kernel */
436 40 0.0014 : sf_state->thread2.scratch_space_base_pointer = 0;
437 : sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
438 13800 0.4925 : sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
439 988 0.0353 : sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
440 : /* don't smash vertex header, read start from dw8 */
441 2292 0.0818 : sf_state->thread3.urb_entry_read_offset = 1;
442 2819 0.1006 : sf_state->thread3.dispatch_grf_start_reg = 3;
443 20 7.1e-04 : sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
444 1265 0.0451 : sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
445 16395 0.5851 : sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
446 324 0.0116 : sf_state->thread4.stats_enable = 1;
447 978 0.0349 : sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
448 13430 0.4793 : sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
449 1120 0.0400 : sf_state->sf6.scissor = 0;
450 38 0.0014 : sf_state->sf7.trifan_pv = 2;
451 140 0.0050 : sf_state->sf6.dest_org_vbias = 0x8;
452 11266 0.4021 : sf_state->sf6.dest_org_hbias = 0x8;
454 : /* Set up the PS kernel (dispatched by WM) */
455 22 7.9e-04 : if (pMask) {
456 26 9.3e-04 : if (pMaskPicture->componentAlpha &&
457 : PICT_FORMAT_RGB(pMaskPicture->format)) {
458 38 0.0014 : if (i965_blend_op[op].src_alpha)
459 148 0.0053 : memcpy(ps_kernel, ps_kernel_static_maskca_srcalpha,
460 : sizeof (ps_kernel_static_maskca_srcalpha));
462 48 0.0017 : memcpy(ps_kernel, ps_kernel_static_maskca,
463 : sizeof (ps_kernel_static_maskca));
465 23 8.2e-04 : memcpy(ps_kernel, ps_kernel_static_masknoca,
466 : sizeof (ps_kernel_static_masknoca));
467 74 0.0026 : } else if (rotation_program) {
468 63 0.0022 : memcpy(ps_kernel, ps_kernel_static_rotation,
469 : sizeof (ps_kernel_static_rotation));
471 10 3.6e-04 : memcpy(ps_kernel, ps_kernel_static_nomask,
472 : sizeof (ps_kernel_static_nomask));
475 549 0.0196 : memset(wm_state, 0, sizeof (*wm_state));
476 29001 1.0350 : wm_state->thread0.kernel_start_pointer =
477 : (state_base_offset + ps_kernel_offset) >> 6;
478 12982 0.4633 : wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
479 : wm_state->thread1.single_program_flow = 1;
481 3871 0.1382 : wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
483 4843 0.1728 : wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
485 8578 0.3061 : wm_state->thread2.scratch_space_base_pointer = (state_base_offset +
486 : wm_scratch_offset)>>10;
487 13261 0.4733 : wm_state->thread2.per_thread_scratch_space = 0;
488 : wm_state->thread3.const_urb_entry_read_length = 0;
489 5646 0.2015 : wm_state->thread3.const_urb_entry_read_offset = 0;
490 : /* Each pair of attributes (src/mask coords) is one URB entry */
492 2958 0.1056 : wm_state->thread3.urb_entry_read_length = 2;
494 2386 0.0852 : wm_state->thread3.urb_entry_read_length = 1;
495 30 0.0011 : wm_state->thread3.urb_entry_read_offset = 0;
496 : /* wm kernel use urb from 3, see wm_program in compiler module */
497 13080 0.4668 : wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
499 12997 0.4638 : wm_state->wm4.stats_enable = 1; /* statistic */
500 79 0.0028 : wm_state->wm4.sampler_state_pointer = (state_base_offset +
501 : src_sampler_offset) >> 5;
502 10829 0.3865 : wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
503 40 0.0014 : wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
504 2 7.1e-05 : wm_state->wm5.thread_dispatch_enable = 1;
505 : /* just use 16-pixel dispatch (4 subspans), don't need to change kernel
508 93 0.0033 : wm_state->wm5.enable_16_pix = 1;
509 : wm_state->wm5.enable_8_pix = 0;
510 10969 0.3915 : wm_state->wm5.early_depth_test = 1;
512 : /* Begin the long sequence of commands needed to set up the 3D
516 111 0.0040 : BEGIN_LP_RING(2);
517 21 7.5e-04 : OUT_RING(MI_FLUSH |
518 : MI_STATE_INSTRUCTION_CACHE_FLUSH |
519 : BRW_MI_GLOBAL_SNAPSHOT_RESET);
520 39 0.0014 : OUT_RING(MI_NOOP);
521 239 0.0085 : ADVANCE_LP_RING();
524 5017 0.1790 : BEGIN_LP_RING(12);
526 : /* Match Mesa driver setup */
527 57 0.0020 : OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
529 130 0.0046 : OUT_RING(BRW_CS_URB_STATE | 0);
530 136 0.0049 : OUT_RING((0 << 4) | /* URB Entry Allocation Size */
531 : (0 << 0)); /* Number of URB Entries */
533 : /* Zero out the two base address registers so all offsets are
536 71 0.0025 : OUT_RING(BRW_STATE_BASE_ADDRESS | 4);
537 79 0.0028 : OUT_RING(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
538 68 0.0024 : OUT_RING(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
539 167 0.0060 : OUT_RING(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
540 : /* general state max addr, disabled */
541 62 0.0022 : OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
542 : /* media object state max addr, disabled */
543 60 0.0021 : OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
545 : /* Set system instruction pointer */
546 159 0.0057 : OUT_RING(BRW_STATE_SIP | 0);
547 223 0.0080 : OUT_RING(state_base_offset + sip_kernel_offset);
548 137 0.0049 : OUT_RING(MI_NOOP);
549 1438 0.0513 : ADVANCE_LP_RING();
552 16676 0.5951 : BEGIN_LP_RING(26);
554 53 0.0019 : OUT_RING(BRW_PIPE_CONTROL |
555 : BRW_PIPE_CONTROL_NOWRITE |
556 : BRW_PIPE_CONTROL_IS_FLUSH |
558 181 0.0065 : OUT_RING(0); /* Destination address */
559 62 0.0022 : OUT_RING(0); /* Immediate data low DW */
560 127 0.0045 : OUT_RING(0); /* Immediate data high DW */
562 : /* Binding table pointers */
563 77 0.0027 : OUT_RING(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
564 60 0.0021 : OUT_RING(0); /* vs */
565 90 0.0032 : OUT_RING(0); /* gs */
566 57 0.0020 : OUT_RING(0); /* clip */
567 160 0.0057 : OUT_RING(0); /* sf */
568 : /* Only the PS uses the binding table */
569 200 0.0071 : OUT_RING(state_base_offset + binding_table_offset); /* ps */
571 : /* The drawing rectangle clipping is always on. Set it to values that
572 : * shouldn't do any clipping.
574 282 0.0101 : OUT_RING(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
575 156 0.0056 : OUT_RING(0x00000000); /* ymin, xmin */
576 640 0.0228 : OUT_RING(DRAW_YMAX(pDst->drawable.height - 1) |
577 : DRAW_XMAX(pDst->drawable.width - 1)); /* ymax, xmax */
578 463 0.0165 : OUT_RING(0x00000000); /* yorigin, xorigin */
580 : /* skip the depth buffer */
581 : /* skip the polygon stipple */
582 : /* skip the polygon stipple offset */
583 : /* skip the line stipple */
585 : /* Set the pointers to the 3d pipeline state */
586 132 0.0047 : OUT_RING(BRW_3DSTATE_PIPELINED_POINTERS | 5);
587 529 0.0189 : OUT_RING(state_base_offset + vs_offset); /* 32 byte aligned */
588 181 0.0065 : OUT_RING(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
589 3012 0.1075 : OUT_RING(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
590 4257 0.1519 : OUT_RING(state_base_offset + sf_offset); /* 32 byte aligned */
591 423 0.0151 : OUT_RING(state_base_offset + wm_offset); /* 32 byte aligned */
592 224 0.0080 : OUT_RING(state_base_offset + cc_offset); /* 64 byte aligned */
595 31 0.0011 : OUT_RING(BRW_URB_FENCE |
602 522 0.0186 : OUT_RING(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
603 : ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
604 : ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
605 466 0.0166 : OUT_RING(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
606 : ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
608 : /* Constant buffer state */
609 180 0.0064 : OUT_RING(BRW_CS_URB_STATE | 0);
610 31 0.0011 : OUT_RING(((URB_CS_ENTRY_SIZE - 1) << 4) |
611 : (URB_CS_ENTRIES << 0));
612 1134 0.0405 : ADVANCE_LP_RING();
615 10119 0.3611 : int nelem = pMask ? 3: 2;
616 1022 0.0365 : BEGIN_LP_RING(pMask?12:10);
617 : /* Set up the pointer to our vertex buffer */
618 64 0.0023 : OUT_RING(BRW_3DSTATE_VERTEX_BUFFERS | 3);
619 61 0.0022 : OUT_RING((0 << VB0_BUFFER_INDEX_SHIFT) |
621 : ((4 * 2 * nelem) << VB0_BUFFER_PITCH_SHIFT));
622 119 0.0042 : OUT_RING(state_base_offset + vb_offset);
623 35 0.0012 : OUT_RING(3);
624 94 0.0034 : OUT_RING(0); // ignore for VERTEXDATA, but still there
626 : /* Set up our vertex elements, sourced from the single vertex buffer.
628 64 0.0023 : OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));
629 : /* vertex coordinates */
630 65 0.0023 : OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
632 : (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
633 : (0 << VE0_OFFSET_SHIFT));
634 33 0.0012 : OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
635 : (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
636 : (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
637 : (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
638 : (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
640 45 0.0016 : OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
642 : (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
643 : (8 << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
644 151 0.0054 : OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
645 : (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
646 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
647 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
648 : (8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
650 42 0.0015 : if (pMask) {
651 35 0.0012 : OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
653 : (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
654 : (16 << VE0_OFFSET_SHIFT));
655 31 0.0011 : OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
656 : (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
657 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
658 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
659 : (10 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
662 1064 0.0380 : ADVANCE_LP_RING();
666 : ErrorF("try to sync to show any errors...");