2 * Command line: opannotate --source --assembly
4 * Interpretation of command line:
5 * Output annotated assembly listing with samples
7 * CPU: Core 2, speed 2133.49 MHz (estimated)
8 * Counted CPU_CLK_UNHALTED events (Clock cycles when not halted) with a unit mask of 0x00 (Unhalted core cycles) count 100000
11 :/home/cworth/opt/xorg/lib/xorg/modules/drivers/intel_drv.so: file format elf32-i386
13 :Disassembly of section .init:
14 :Disassembly of section .plt:
15 :Disassembly of section .text:
17 00032e90 <i965_prepare_composite>: /* i965_prepare_composite total: 830728 29.6474 */
19 :i965_prepare_composite(int op, PicturePtr pSrcPicture,
20 : PicturePtr pMaskPicture, PicturePtr pDstPicture,
21 : PixmapPtr pSrc, PixmapPtr pMask, PixmapPtr pDst)
23 79 0.0028 : 32e90: push %ebp
24 56 0.0020 : 32e91: mov %esp,%ebp
26 33 0.0012 : 32e94: push %esi
27 4 1.4e-04 : 32e95: push %ebx
28 10 3.6e-04 : 32e96: sub $0x8c,%esp
29 : ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
30 24 8.6e-04 : 32e9c: mov 0xc(%ebp),%edx
31 34 0.0012 : 32e9f: call 8c27 <__i686.get_pc_thunk.bx>
32 88 0.0031 : 32ea4: add $0x12968,%ebx
33 24 8.6e-04 : 32eaa: mov (%edx),%eax
34 32 0.0011 : 32eac: mov 0xffffff70(%ebx),%edx
35 276 0.0099 : 32eb2: mov 0x10(%eax),%eax
36 23 8.2e-04 : 32eb5: mov (%eax),%eax
37 86 0.0031 : 32eb7: shl $0x2,%eax
38 20 7.1e-04 : 32eba: add (%edx),%eax
39 252 0.0090 : 32ebc: mov (%eax),%eax
40 280 0.0100 : 32ebe: mov %eax,0xffffff98(%ebp)
41 : I830Ptr pI830 = I830PTR(pScrn);
42 54 0.0019 : 32ec1: mov 0xf8(%eax),%ecx
43 130 0.0046 : 32ec7: mov %ecx,0xffffff9c(%ebp)
44 : CARD32 src_offset, src_pitch;
45 : CARD32 mask_offset = 0, mask_pitch = 0;
46 : CARD32 dst_format, dst_offset, dst_pitch;
47 : Bool rotation_program = FALSE;
49 : IntelEmitInvarientState(pScrn);
50 22 7.9e-04 : 32eca: mov %eax,(%esp)
51 : 32ecd: call 75e8 <IntelEmitInvarientState@plt>
52 : *pI830->last_3d = LAST_3D_RENDER;
53 32 0.0011 : 32ed2: mov 0xffffff9c(%ebp),%esi
54 17 6.1e-04 : 32ed5: mov 0xc30(%esi),%eax
55 54 0.0019 : 32edb: movl $0x2,(%eax)
57 : src_offset = intel_get_pixmap_offset(pSrc);
58 70 0.0025 : 32ee1: mov 0x18(%ebp),%eax
59 68 0.0024 : 32ee4: mov %eax,(%esp)
60 11 3.9e-04 : 32ee7: call 8558 <intel_get_pixmap_offset@plt>
61 : src_pitch = intel_get_pixmap_pitch(pSrc);
62 21 7.5e-04 : 32eec: mov 0x18(%ebp),%edx
63 4 1.4e-04 : 32eef: mov %eax,0xffffffa0(%ebp)
64 11 3.9e-04 : 32ef2: mov %edx,(%esp)
65 29 0.0010 : 32ef5: call 7728 <intel_get_pixmap_pitch@plt>
66 : dst_offset = intel_get_pixmap_offset(pDst);
67 34 0.0012 : 32efa: mov 0x20(%ebp),%ecx
68 4 1.4e-04 : 32efd: mov %eax,0xffffffa4(%ebp)
69 16 5.7e-04 : 32f00: mov %ecx,(%esp)
70 109 0.0039 : 32f03: call 8558 <intel_get_pixmap_offset@plt>
71 : dst_pitch = intel_get_pixmap_pitch(pDst);
72 27 9.6e-04 : 32f08: mov 0x20(%ebp),%esi
73 1 3.6e-05 : 32f0b: mov %eax,0xffffffb0(%ebp)
74 7 2.5e-04 : 32f0e: mov %esi,(%esp)
75 38 0.0014 : 32f11: call 7728 <intel_get_pixmap_pitch@plt>
77 25 8.9e-04 : 32f16: mov 0x1c(%ebp),%ecx
78 : 32f19: test %ecx,%ecx
79 : 32f1b: mov %eax,0xffffffb4(%ebp)
80 : 32f1e: je 338d0 <i965_prepare_composite+0xa40>
81 : mask_offset = intel_get_pixmap_offset(pMask);
82 20 7.1e-04 : 32f24: mov 0x1c(%ebp),%eax
83 5 1.8e-04 : 32f27: mov %eax,(%esp)
84 2 7.1e-05 : 32f2a: call 8558 <intel_get_pixmap_offset@plt>
85 : mask_pitch = intel_get_pixmap_pitch(pMask);
86 12 4.3e-04 : 32f2f: mov 0x1c(%ebp),%edx
87 : 32f32: mov %eax,0xffffffa8(%ebp)
88 : 32f35: mov %edx,(%esp)
89 16 5.7e-04 : 32f38: call 7728 <intel_get_pixmap_pitch@plt>
91 : pI830->scale_units[0][0] = pSrc->drawable.width;
92 18 6.4e-04 : 32f3d: mov 0x18(%ebp),%ecx
93 : 32f40: mov %eax,0xffffffac(%ebp)
94 8 2.9e-04 : 32f43: movzwl 0xc(%ecx),%eax
95 4 1.4e-04 : 32f47: push %eax
96 15 5.4e-04 : 32f48: mov 0xffffff9c(%ebp),%esi
97 18 6.4e-04 : 32f4b: fildl (%esp)
98 23 8.2e-04 : 32f4e: fstps 0x264(%esi)
99 : pI830->scale_units[0][1] = pSrc->drawable.height;
100 16 5.7e-04 : 32f54: movzwl 0xe(%ecx),%eax
101 4 1.4e-04 : 32f58: mov %eax,(%esp)
102 : 32f5b: fildl (%esp)
103 6 2.1e-04 : 32f5e: fstps 0x268(%esi)
105 : pI830->transform[0] = pSrcPicture->transform;
106 17 6.1e-04 : 32f64: mov 0xc(%ebp),%edx
107 1 3.6e-05 : 32f67: mov 0x40(%edx),%eax
108 37 0.0013 : 32f6a: mov %eax,0x274(%esi)
111 : pI830->transform[1] = NULL;
112 : pI830->scale_units[1][0] = -1;
113 : pI830->scale_units[1][1] = -1;
114 : if (pI830->transform[0] &&
115 : i965_check_rotation_transform(pI830->transform[0]))
116 : rotation_program = TRUE;
118 : pI830->transform[1] = pMaskPicture->transform;
119 8 2.9e-04 : 32f70: mov 0x10(%ebp),%ecx
120 15 5.4e-04 : 32f73: mov 0x40(%ecx),%eax
121 21 7.5e-04 : 32f76: mov %eax,0x278(%esi)
122 : pI830->scale_units[1][0] = pMask->drawable.width;
123 8 2.9e-04 : 32f7c: mov 0x1c(%ebp),%esi
124 : 32f7f: movzwl 0xc(%esi),%eax
125 32 0.0011 : 32f83: mov %eax,(%esp)
126 1 3.6e-05 : 32f86: mov 0xffffff9c(%ebp),%eax
127 3 1.1e-04 : 32f89: fildl (%esp)
128 81 0.0029 : 32f8c: fstps 0x26c(%eax)
129 : pI830->scale_units[1][1] = pMask->drawable.height;
130 10 3.6e-04 : 32f92: movzwl 0xe(%esi),%eax
131 4 1.4e-04 : 32f96: mov %eax,(%esp)
132 9 3.2e-04 : 32f99: mov 0xffffff9c(%ebp),%edx
133 5 1.8e-04 : 32f9c: fildl (%esp)
134 71 0.0025 : 32f9f: add $0x4,%esp
135 : 32fa2: fstps 0x270(%edx)
138 : /* setup 3d pipeline state */
140 : binding_table_entries = 2; /* default no mask */
141 12 4.3e-04 : 32fa8: movl $0x2,0x2a04(%ebx)
143 : /* Wait for sync before we start setting up our new state */
145 : i830WaitSync(pScrn);
148 : /* Set up our layout of state in framebuffer. First the general state: */
150 : vs_offset = ALIGN(next_offset, 64);
151 4 1.4e-04 : 32fb2: movl $0x0,0x2a1c(%ebx)
152 : next_offset = vs_offset + sizeof(*vs_state);
154 : sf_offset = ALIGN(next_offset, 32);
155 3 1.1e-04 : 32fbc: movl $0x20,0x2a20(%ebx)
156 : next_offset = sf_offset + sizeof(*sf_state);
158 : wm_offset = ALIGN(next_offset, 32);
159 11 3.9e-04 : 32fc6: movl $0x40,0x2a24(%ebx)
160 : next_offset = wm_offset + sizeof(*wm_state);
162 : wm_scratch_offset = ALIGN(next_offset, 1024);
163 6 2.1e-04 : 32fd0: movl $0x400,0x2a40(%ebx)
164 : next_offset = wm_scratch_offset + 1024 * PS_MAX_THREADS;
166 : cc_offset = ALIGN(next_offset, 32);
167 30 0.0011 : 32fda: movl $0x8400,0x2a28(%ebx)
168 : next_offset = cc_offset + sizeof(*cc_state);
170 : /* keep current sf_kernel, which will send one setup urb entry to
173 : sf_kernel_offset = ALIGN(next_offset, 64);
175 : next_offset = sf_kernel_offset + sizeof (sf_kernel_static_mask);
176 14 5.0e-04 : 32fe4: movl $0x85d0,0x2a4c(%ebx)
177 1 3.6e-05 : 32fee: movl $0x8440,0x2a34(%ebx)
178 : else if (rotation_program)
179 : next_offset = sf_kernel_offset + sizeof (sf_kernel_static_rotation);
181 : next_offset = sf_kernel_offset + sizeof (sf_kernel_static);
183 : ps_kernel_offset = ALIGN(next_offset, 64);
184 6 2.1e-04 : 32ff8: movl $0x8600,0x2a38(%ebx)
186 : if (pMaskPicture->componentAlpha &&
187 : PICT_FORMAT_RGB(pMaskPicture->format)) {
188 : if (i965_blend_op[op].src_alpha) {
189 : next_offset = ps_kernel_offset +
190 : sizeof(ps_kernel_static_maskca_srcalpha);
192 : next_offset = ps_kernel_offset +
193 : sizeof(ps_kernel_static_maskca);
196 : next_offset = ps_kernel_offset +
197 94 0.0034 : 33002: movl $0x8bf0,0x2a4c(%ebx)
198 12 4.3e-04 : 3300c: movl $0x8600,0xffffffc0(%ebp)
199 8 2.9e-04 : 33013: movl $0x0,0xffffffb8(%ebp)
200 : sizeof(ps_kernel_static_masknoca);
201 : } else if (rotation_program) {
202 : next_offset = ps_kernel_offset + sizeof (ps_kernel_static_rotation);
204 : next_offset = ps_kernel_offset + sizeof (ps_kernel_static_nomask);
207 : sip_kernel_offset = ALIGN(next_offset, 64);
208 33 0.0012 : 3301a: mov 0x2a4c(%ebx),%ecx
209 : next_offset = sip_kernel_offset + sizeof (sip_kernel_static);
212 : cc_viewport_offset = ALIGN(next_offset, 32);
213 : next_offset = cc_viewport_offset + sizeof(*cc_viewport);
215 : /* for texture sampler */
216 : src_sampler_offset = ALIGN(next_offset, 32);
217 : next_offset = src_sampler_offset + sizeof(*src_sampler_state);
220 69 0.0025 : 33020: mov 0x1c(%ebp),%edx
221 93 0.0033 : 33023: add $0x3f,%ecx
222 8 2.9e-04 : 33026: and $0xffffffc0,%ecx
223 22 7.9e-04 : 33029: mov %ecx,0xffffff88(%ebp)
224 42 0.0015 : 3302c: mov %ecx,0x2a3c(%ebx)
225 65 0.0023 : 33032: add $0xa0,%ecx
226 1 3.6e-05 : 33038: mov %ecx,0xffffff8c(%ebp)
227 31 0.0011 : 3303b: mov %ecx,0x2a30(%ebx)
228 35 0.0012 : 33041: add $0x20,%ecx
229 2 7.1e-05 : 33044: mov %ecx,%eax
230 : 33046: add $0x10,%eax
231 16 5.7e-04 : 33049: test %edx,%edx
232 18 6.4e-04 : 3304b: mov %ecx,0xffffffd0(%ebp)
233 19 6.8e-04 : 3304e: mov %ecx,0x2a14(%ebx)
234 28 1.0e-03 : 33054: mov %eax,0x2a4c(%ebx)
235 27 9.6e-04 : 3305a: je 3306e <i965_prepare_composite+0x1de>
236 : mask_sampler_offset = ALIGN(next_offset, 32);
237 1 3.6e-05 : 3305c: add $0x10,%eax
238 13 4.6e-04 : 3305f: mov %eax,0x2a18(%ebx)
239 : next_offset = mask_sampler_offset + sizeof(*mask_sampler_state);
240 31 0.0011 : 33065: add $0x10,%eax
241 : 33068: mov %eax,0x2a4c(%ebx)
243 : /* Align VB to native size of elements, for safety */
244 : vb_offset = ALIGN(next_offset, 8);
245 41 0.0015 : 3306e: mov 0x2a4c(%ebx),%esi
246 211 0.0075 : 33074: add $0x7,%esi
247 22 7.9e-04 : 33077: and $0xfffffff8,%esi
248 : next_offset = vb_offset + vb_size;
250 : /* And then the general state: */
251 : dest_surf_offset = ALIGN(next_offset, 32);
252 32 0.0011 : 3307a: mov %esi,%ecx
253 36 0.0013 : 3307c: add $0x5f,%ecx
254 27 9.6e-04 : 3307f: and $0xffffffe0,%ecx
255 : next_offset = dest_surf_offset + sizeof(*dest_surf_state);
257 : src_surf_offset = ALIGN(next_offset, 32);
258 75 0.0027 : 33082: lea 0x20(%ecx),%eax
259 31 0.0011 : 33085: mov %eax,0xffffffd4(%ebp)
260 30 0.0011 : 33088: mov %eax,0x2a0c(%ebx)
261 : next_offset = src_surf_offset + sizeof(*src_surf_state);
262 40 0.0014 : 3308e: add $0x14,%eax
263 350 0.0125 : 33091: mov %eax,0x2a4c(%ebx)
266 26 9.3e-04 : 33097: mov 0x1c(%ebp),%eax
267 33 0.0012 : 3309a: mov %esi,0xffffff90(%ebp)
268 30 0.0011 : 3309d: mov %esi,0x2a2c(%ebx)
269 89 0.0032 : 330a3: mov %ecx,0x2a08(%ebx)
270 29 0.0010 : 330a9: test %eax,%eax
271 : 330ab: je 330cc <i965_prepare_composite+0x23c>
272 : mask_surf_offset = ALIGN(next_offset, 32);
273 1 3.6e-05 : 330ad: mov 0xffffffd4(%ebp),%eax
274 : next_offset = mask_surf_offset + sizeof(*mask_surf_state);
275 : binding_table_entries = 3;
276 9 3.2e-04 : 330b0: movl $0x3,0x2a04(%ebx)
277 13 4.6e-04 : 330ba: add $0x20,%eax
278 14 5.0e-04 : 330bd: mov %eax,0x2a10(%ebx)
279 28 1.0e-03 : 330c3: add $0x14,%eax
280 : 330c6: mov %eax,0x2a4c(%ebx)
283 : binding_table_offset = ALIGN(next_offset, 32);
284 25 8.9e-04 : 330cc: mov 0x2a4c(%ebx),%edi
285 : next_offset = binding_table_offset + (binding_table_entries * 4);
287 : default_color_offset = ALIGN(next_offset, 32);
288 101 0.0036 : 330d2: mov 0x2a04(%ebx),%eax
289 : next_offset = default_color_offset + sizeof(*default_color_state);
291 : total_state_size = next_offset;
292 : assert(total_state_size < pI830->exa_965_state->size);
294 : state_base_offset = pI830->exa_965_state->offset;
295 39 0.0014 : 330d8: mov 0xffffff9c(%ebp),%edx
296 4 1.4e-04 : 330db: add $0x1f,%edi
297 28 1.0e-03 : 330de: and $0xffffffe0,%edi
298 26 9.3e-04 : 330e1: lea 0x1f(%edi,%eax,4),%esi
299 28 1.0e-03 : 330e5: and $0xffffffe0,%esi
300 35 0.0012 : 330e8: lea 0x10(%esi),%eax
301 27 9.6e-04 : 330eb: mov %edi,0x2a44(%ebx)
302 : 330f1: mov %esi,0x2a48(%ebx)
303 8 2.9e-04 : 330f7: mov %eax,0x2a4c(%ebx)
304 36 0.0013 : 330fd: mov %eax,0x2a50(%ebx)
305 64 0.0023 : 33103: mov 0x68(%edx),%eax
306 : state_base_offset = ALIGN(state_base_offset, 64);
307 35 0.0012 : 33106: mov (%eax),%edx
308 : state_base = (char *)(pI830->FbBase + state_base_offset);
309 157 0.0056 : 33108: mov 0xffffff9c(%ebp),%eax
310 10 3.6e-04 : 3310b: add $0x3f,%edx
311 23 8.2e-04 : 3310e: and $0xffffffc0,%edx
312 16 5.7e-04 : 33111: mov %edx,0x2a58(%ebx)
313 14 5.0e-04 : 33117: add 0x8(%eax),%edx
315 : vs_state = (void *)(state_base + vs_offset);
316 : sf_state = (void *)(state_base + sf_offset);
317 11 3.9e-04 : 3311a: lea 0x20(%edx),%eax
318 25 8.9e-04 : 3311d: mov %eax,0x29e4(%ebx)
319 : wm_state = (void *)(state_base + wm_offset);
320 39 0.0014 : 33123: lea 0x40(%edx),%eax
321 4 1.4e-04 : 33126: mov %eax,0x29e8(%ebx)
322 : cc_state = (void *)(state_base + cc_offset);
323 34 0.0012 : 3312c: lea 0x8400(%edx),%eax
324 4 1.4e-04 : 33132: mov %eax,0x29ec(%ebx)
325 : sf_kernel = (void *)(state_base + sf_kernel_offset);
326 29 0.0010 : 33138: lea 0x8440(%edx),%eax
327 : 3313e: mov %eax,0x29f4(%ebx)
328 : ps_kernel = (void *)(state_base + ps_kernel_offset);
329 54 0.0019 : 33144: mov 0xffffffc0(%ebp),%eax
330 2 7.1e-05 : 33147: mov %edx,0x2a54(%ebx)
331 12 4.3e-04 : 3314d: mov %edx,0x29e0(%ebx)
332 10 3.6e-04 : 33153: add %edx,%eax
333 15 5.4e-04 : 33155: mov %eax,0x29f8(%ebx)
334 : sip_kernel = (void *)(state_base + sip_kernel_offset);
335 11 3.9e-04 : 3315b: mov 0xffffff88(%ebp),%eax
336 14 5.0e-04 : 3315e: add %edx,%eax
337 6 2.1e-04 : 33160: mov %eax,0x29fc(%ebx)
339 : cc_viewport = (void *)(state_base + cc_viewport_offset);
340 27 9.6e-04 : 33166: mov 0xffffff8c(%ebp),%eax
341 6 2.1e-04 : 33169: add %edx,%eax
342 3 1.1e-04 : 3316b: mov %eax,0xffffff94(%ebp)
343 27 9.6e-04 : 3316e: mov %eax,0x29f0(%ebx)
345 : dest_surf_state = (void *)(state_base + dest_surf_offset);
346 25 8.9e-04 : 33174: lea (%edx,%ecx,1),%eax
347 : src_surf_state = (void *)(state_base + src_surf_offset);
348 4 1.4e-04 : 33177: mov 0xffffffd4(%ebp),%ecx
349 : 3317a: mov %eax,0x29c8(%ebx)
350 12 4.3e-04 : 33180: lea (%edx,%ecx,1),%eax
351 48 0.0017 : 33183: mov %eax,0x29cc(%ebx)
353 27 9.6e-04 : 33189: mov 0x1c(%ebp),%eax
354 2 7.1e-05 : 3318c: test %eax,%eax
355 8 2.9e-04 : 3318e: je 34240 <i965_prepare_composite+0x13b0>
356 : mask_surf_state = (void *)(state_base + mask_surf_offset);
358 : src_sampler_state = (void *)(state_base + src_sampler_offset);
359 : 33194: mov 0xffffffd0(%ebp),%ecx
360 8 2.9e-04 : 33197: mov %edx,%eax
361 8 2.9e-04 : 33199: add 0x2a10(%ebx),%eax
362 1 3.6e-05 : 3319f: mov %eax,0x29d0(%ebx)
363 8 2.9e-04 : 331a5: lea (%edx,%ecx,1),%eax
364 1 3.6e-05 : 331a8: mov %eax,0x29d4(%ebx)
366 : mask_sampler_state = (void *)(state_base + mask_sampler_offset);
367 14 5.0e-04 : 331ae: mov %edx,%eax
368 2 7.1e-05 : 331b0: add 0x2a18(%ebx),%eax
369 4 1.4e-04 : 331b6: mov %eax,0x29d8(%ebx)
371 : binding_table = (void *)(state_base + binding_table_offset);
373 : vb = (void *)(state_base + vb_offset);
374 21 7.5e-04 : 331bc: mov 0xffffff90(%ebp),%ecx
375 33 0.0012 : 331bf: lea (%edx,%edi,1),%eax
376 22 7.9e-04 : 331c2: mov %eax,0x2a00(%ebx)
378 : default_color_state = (void*)(state_base + default_color_offset);
380 : /* Set up a default static partitioning of the URB, which is supposed to
381 : * allow anything we would want to do, at potentially lower performance.
383 :#define URB_CS_ENTRY_SIZE 0
384 :#define URB_CS_ENTRIES 0
386 :#define URB_VS_ENTRY_SIZE 1 // each 512-bit row
387 :#define URB_VS_ENTRIES 8 // we needs at least 8 entries
389 :#define URB_GS_ENTRY_SIZE 0
390 :#define URB_GS_ENTRIES 0
392 :#define URB_CLIP_ENTRY_SIZE 0
393 :#define URB_CLIP_ENTRIES 0
395 :#define URB_SF_ENTRY_SIZE 2
396 :#define URB_SF_ENTRIES 1
399 25 8.9e-04 : 331c8: movl $0x0,0x29a0(%ebx)
400 : urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
401 21 7.5e-04 : 331d2: movl $0x8,0x29a4(%ebx)
402 19 6.8e-04 : 331dc: lea (%edx,%ecx,1),%eax
403 : urb_gs_start = urb_vs_start + urb_vs_size;
404 : urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
405 : urb_clip_start = urb_gs_start + urb_gs_size;
406 : urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
407 : urb_sf_start = urb_clip_start + urb_clip_size;
408 : urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
409 : urb_cs_start = urb_sf_start + urb_sf_size;
410 : urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
412 : /* Because we only have a single static buffer for our state currently,
413 : * we have to sync before updating it every time.
416 : i830WaitSync(pScrn);
419 : memset (cc_viewport, 0, sizeof (*cc_viewport));
420 : cc_viewport->min_depth = -1.e35;
421 : cc_viewport->max_depth = 1.e35;
423 : /* Color calculator state */
424 : memset(cc_state, 0, sizeof(*cc_state));
425 : 331df: mov $0x8,%ecx
426 2 7.1e-05 : 331e4: mov %eax,0x2a5c(%ebx)
427 32 0.0011 : 331ea: lea (%edx,%esi,1),%eax
428 1 3.6e-05 : 331ed: mov 0xffffff94(%ebp),%esi
429 33 0.0012 : 331f0: mov %eax,0x29dc(%ebx)
430 40 0.0014 : 331f6: movl $0x8,0x29a8(%ebx)
431 58 0.0021 : 33200: movl $0x0,0x29ac(%ebx)
432 58 0.0021 : 3320a: movl $0x8,0x29b0(%ebx)
433 50 0.0018 : 33214: movl $0x0,0x29b4(%ebx)
434 46 0.0016 : 3321e: movl $0x8,0x29b8(%ebx)
435 52 0.0019 : 33228: movl $0x2,0x29bc(%ebx)
436 42 0.0015 : 33232: movl $0xa,0x29c0(%ebx)
437 43 0.0015 : 3323c: movl $0x0,0x29c4(%ebx)
438 92 0.0033 : 33246: movl $0x0,(%esi)
439 181 0.0065 : 3324c: movl $0x0,0x4(%esi)
440 87 0.0031 : 33253: mov 0x29f0(%ebx),%eax
441 114 0.0041 : 33259: cld
442 37 0.0013 : 3325a: movl $0xf99a130c,(%eax)
443 122 0.0044 : 33260: movl $0x799a130c,0x4(%eax)
444 41 0.0015 : 33267: mov 0x29ec(%ebx),%edi
445 15 5.4e-04 : 3326d: xor %eax,%eax
446 691 0.0247 : 3326f: rep stos %eax,%es:(%edi)
447 : cc_state->cc0.stencil_enable = 0; /* disable stencil */
448 391 0.0140 : 33271: mov 0x29ec(%ebx),%ecx
449 : cc_state->cc2.depth_test = 0; /* disable depth test */
450 : cc_state->cc2.logicop_enable = 0; /* disable logic op */
451 : cc_state->cc3.ia_blend_enable = 1; /* blend alpha just like colors */
452 : cc_state->cc3.blend_enable = 1; /* enable color blend */
453 1 3.6e-05 : 33277: movzbl 0xd(%ecx),%eax
454 18168 0.6484 : 3327b: andb $0x7f,0x3(%ecx)
455 17836 0.6365 : 3327f: andb $0x7f,0x9(%ecx)
456 12306 0.4392 : 33283: andb $0xfe,0x8(%ecx)
457 7307 0.2608 : 33287: or $0x30,%eax
458 : cc_state->cc3.alpha_test = 0; /* disable alpha test */
459 : 3328a: and $0xfffffff7,%eax
460 10 3.6e-04 : 3328d: mov %al,0xd(%ecx)
461 : cc_state->cc4.cc_viewport_state_offset = (state_base_offset +
462 : 33290: mov 0x10(%ecx),%eax
463 9589 0.3422 : 33293: mov 0x2a30(%ebx),%edx
464 : 33299: add 0x2a58(%ebx),%edx
465 1 3.6e-05 : 3329f: and $0x1f,%eax
466 26 9.3e-04 : 332a2: and $0xffffffe0,%edx
467 6 2.1e-04 : 332a5: or %edx,%eax
468 23 8.2e-04 : 332a7: mov %eax,0x10(%ecx)
469 : cc_viewport_offset) >> 5;
470 : cc_state->cc5.dither_enable = 0; /* disable dither */
471 : cc_state->cc5.logicop_func = 0xc; /* COPY */
472 30 0.0011 : 332aa: movzbl 0x16(%ecx),%eax
473 7354 0.2625 : 332ae: andb $0x7f,0x17(%ecx)
474 839 0.0299 : 332b2: and $0xfffffff0,%eax
475 31 0.0011 : 332b5: or $0xc,%eax
476 26 9.3e-04 : 332b8: mov %al,0x16(%ecx)
477 : cc_state->cc5.statistics_enable = 1;
478 28 1.0e-03 : 332bb: movzbl 0x15(%ecx),%eax
479 2752 0.0982 : 332bf: or $0xffffff80,%eax
480 : cc_state->cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD;
481 55 0.0020 : 332c2: and $0xffffff8f,%eax
482 8 2.9e-04 : 332c5: mov %al,0x15(%ecx)
483 : i965_get_blend_cntl(op, pMaskPicture, pDstPicture->format,
484 29 0.0010 : 332c8: mov 0x14(%ebp),%eax
485 4 1.4e-04 : 332cb: mov 0x8(%ebp),%esi
486 3 1.1e-04 : 332ce: mov 0x8(%eax),%edx
487 2 7.1e-05 : 332d1: shl $0x4,%esi
488 25 8.9e-04 : 332d4: mov 0xffffb0fc(%ebx,%esi,1),%edi
489 30 0.0011 : 332db: mov 0xffffb100(%ebx,%esi,1),%eax
490 : 332e2: and $0xf0,%dh
491 : 332e5: mov %edi,0x2a60(%ebx)
492 26 9.3e-04 : 332eb: mov %eax,0x2a64(%ebx)
493 8 2.9e-04 : 332f1: jne 33302 <i965_prepare_composite+0x472>
494 : 332f3: mov 0xffffb0f4(%ebx,%esi,1),%eax
495 : 332fa: test %eax,%eax
496 21 7.5e-04 : 332fc: jne 33880 <i965_prepare_composite+0x9f0>
497 24 8.6e-04 : 33302: mov 0x10(%ebp),%edi
498 5 1.8e-04 : 33305: test %edi,%edi
499 : 33307: je 33316 <i965_prepare_composite+0x486>
500 : 33309: mov 0x10(%ebp),%edx
501 19 6.8e-04 : 3330c: testb $0x1,0x19(%edx)
502 4 1.4e-04 : 33310: jne 33790 <i965_prepare_composite+0x900>
503 : &src_blend, &dst_blend);
504 : /* XXX: alpha blend factor should be same as color, but check
505 : * for CA case in future
507 : cc_state->cc5.ia_src_blend_factor = src_blend;
508 42 0.0015 : 33316: movzbl 0x2a60(%ebx),%edx
509 22 7.9e-04 : 3331d: movzwl 0x14(%ecx),%eax
510 13919 0.4967 : 33321: and $0x1f,%edx
511 : 33324: and $0x1f,%edx
512 : 33327: and $0xf07f,%ax
513 36 0.0013 : 3332b: shl $0x7,%edx
514 : 3332e: or %edx,%eax
515 70 0.0025 : 33330: mov %ax,0x14(%ecx)
516 : cc_state->cc5.ia_dest_blend_factor = dst_blend;
517 37 0.0013 : 33334: movzbl 0x2a64(%ebx),%edx
518 : 3333b: movzbl 0x14(%ecx),%eax
519 : cc_state->cc6.blend_function = BRW_BLENDFUNCTION_ADD;
520 13845 0.4941 : 3333f: andb $0x1f,0x1b(%ecx)
521 215 0.0077 : 33343: and $0x1f,%edx
522 : 33346: shl $0x2,%edx
523 32 0.0011 : 33349: and $0xffffff83,%eax
524 2 7.1e-05 : 3334c: or %edx,%eax
525 15 5.4e-04 : 3334e: mov %al,0x14(%ecx)
526 : cc_state->cc6.src_blend_factor = src_blend;
527 31 0.0011 : 33351: movzbl 0x2a60(%ebx),%eax
528 : 33358: and $0x1f,%eax
529 : 3335b: mov %al,0x1b(%ecx)
530 : cc_state->cc6.dest_blend_factor = dst_blend;
531 2 7.1e-05 : 3335e: movzbl 0x2a64(%ebx),%edx
532 34 0.0012 : 33365: movzbl 0x1a(%ecx),%eax
533 2280 0.0814 : 33369: and $0x1f,%edx
534 : 3336c: shl $0x3,%edx
535 : 3336f: and $0x7,%eax
536 27 9.6e-04 : 33372: or %edx,%eax
537 18 6.4e-04 : 33374: mov %al,0x1a(%ecx)
538 : cc_state->cc6.clamp_post_alpha_blend = 1;
539 : cc_state->cc6.clamp_pre_alpha_blend = 1;
540 15 5.4e-04 : 33377: movzbl 0x18(%ecx),%eax
541 4451 0.1588 : 3337b: or $0x3,%eax
542 : cc_state->cc6.clamp_range = 0; /* clamp range [0,1] */
543 25 8.9e-04 : 3337e: and $0xfffffff3,%eax
544 334 0.0119 : 33381: mov %al,0x18(%ecx)
546 : /* Upload system kernel */
547 : memcpy (sip_kernel, sip_kernel_static, sizeof (sip_kernel_static));
548 39 0.0014 : 33384: lea 0xffffb1d4(%ebx),%eax
549 : 3338a: mov %eax,0x4(%esp)
550 23 8.2e-04 : 3338e: mov 0x29fc(%ebx),%eax
551 : 33394: movl $0xa0,0x8(%esp)
552 15 5.4e-04 : 3339c: mov %eax,(%esp)
553 9 3.2e-04 : 3339f: call 7d88 <memcpy@plt>
555 : /* Set up the state buffer for the destination surface */
556 : memset(dest_surf_state, 0, sizeof(*dest_surf_state));
557 47 0.0017 : 333a4: mov 0x29c8(%ebx),%eax
558 : dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
559 : dest_surf_state->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32;
560 : i965_get_dest_format(pDstPicture, &dst_format);
561 2 7.1e-05 : 333aa: lea 0xfffffff0(%ebp),%edx
562 : 333ad: movl $0x0,(%eax)
563 83 0.0030 : 333b3: movl $0x0,0x4(%eax)
564 34 0.0012 : 333ba: movl $0x0,0x8(%eax)
565 144 0.0051 : 333c1: movl $0x0,0xc(%eax)
566 24 8.6e-04 : 333c8: movl $0x0,0x10(%eax)
567 34 0.0012 : 333cf: mov 0x29c8(%ebx),%esi
568 13 4.6e-04 : 333d5: movzbl 0x3(%esi),%eax
569 15244 0.5440 : 333d9: and $0x17,%eax
570 39 0.0014 : 333dc: or $0x20,%eax
571 28 1.0e-03 : 333df: mov %al,0x3(%esi)
572 36 0.0013 : 333e2: mov 0x14(%ebp),%eax
573 1 3.6e-05 : 333e5: call 32810 <i965_get_dest_format>
574 : dest_surf_state->ss0.surface_format = dst_format;
575 86 0.0031 : 333ea: movzwl 0xfffffff0(%ebp),%edx
576 26 9.3e-04 : 333ee: movzwl 0x2(%esi),%eax
577 14220 0.5075 : 333f2: and $0x1ff,%dx
578 : 333f7: shl $0x2,%edx
579 : 333fa: and $0xf803,%ax
580 33 0.0012 : 333fe: or %edx,%eax
581 65 0.0023 : 33400: mov %ax,0x2(%esi)
583 : dest_surf_state->ss0.writedisable_alpha = 0;
584 : dest_surf_state->ss0.writedisable_red = 0;
585 : dest_surf_state->ss0.writedisable_green = 0;
586 : dest_surf_state->ss0.writedisable_blue = 0;
587 : dest_surf_state->ss0.color_blend = 1;
588 23 8.2e-04 : 33404: movzbl 0x1(%esi),%eax
589 361 0.0129 : 33408: andb $0xfc,0x2(%esi)
590 14053 0.5015 : 3340c: and $0x21,%eax
591 : dest_surf_state->ss0.vert_line_stride = 0;
592 : dest_surf_state->ss0.vert_line_stride_ofs = 0;
593 : dest_surf_state->ss0.mipmap_layout_mode = 0;
594 : dest_surf_state->ss0.render_cache_read_mode = 0;
595 : 3340f: or $0x20,%eax
596 : 33412: mov %al,0x1(%esi)
598 : dest_surf_state->ss1.base_addr = dst_offset;
599 : 33415: mov 0xffffffb0(%ebp),%ecx
600 36 0.0013 : 33418: mov %ecx,0x4(%esi)
601 : dest_surf_state->ss2.height = pDst->drawable.height - 1;
602 : 3341b: mov 0x20(%ebp),%eax
603 : 3341e: movzwl 0xe(%eax),%edx
604 : 33422: movzwl 0xa(%esi),%eax
605 387 0.0138 : 33426: sub $0x1,%edx
606 : 33429: shl $0x3,%edx
607 : 3342c: and $0x7,%eax
608 1 3.6e-05 : 3342f: or %edx,%eax
609 32 0.0011 : 33431: mov %ax,0xa(%esi)
610 : dest_surf_state->ss2.width = pDst->drawable.width - 1;
611 1 3.6e-05 : 33435: mov 0x20(%ebp),%ecx
612 : 33438: mov 0x8(%esi),%eax
613 14501 0.5175 : 3343b: movzwl 0xc(%ecx),%edx
614 : 3343f: sub $0x1,%edx
615 2 7.1e-05 : 33442: and $0x1fff,%edx
616 : 33448: and $0xfff8003f,%eax
617 29 0.0010 : 3344d: shl $0x6,%edx
618 1 3.6e-05 : 33450: or %edx,%eax
619 33 0.0012 : 33452: mov %eax,0x8(%esi)
620 : dest_surf_state->ss2.mip_count = 0;
621 : dest_surf_state->ss2.render_target_rotation = 0;
622 : dest_surf_state->ss3.pitch = dst_pitch - 1;
623 45 0.0016 : 33455: mov 0xc(%esi),%eax
624 398 0.0142 : 33458: andb $0xc0,0x8(%esi)
625 11618 0.4146 : 3345c: mov 0xffffffb4(%ebp),%edx
626 : 3345f: and $0xffe00007,%eax
627 : 33464: sub $0x1,%edx
628 : 33467: and $0x3ffff,%edx
629 28 1.0e-03 : 3346d: shl $0x3,%edx
630 : 33470: or %edx,%eax
631 : 33472: mov %eax,0xc(%esi)
633 : /* Set up the source surface state buffer */
634 : memset(src_surf_state, 0, sizeof(*src_surf_state));
635 1 3.6e-05 : 33475: mov 0x29cc(%ebx),%eax
636 37 0.0013 : 3347b: movl $0x0,(%eax)
637 3 1.1e-04 : 33481: movl $0x0,0x4(%eax)
638 : 33488: movl $0x0,0x8(%eax)
639 : 3348f: movl $0x0,0xc(%eax)
640 25 8.9e-04 : 33496: movl $0x0,0x10(%eax)
641 : src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
642 1 3.6e-05 : 3349d: mov 0x29cc(%ebx),%esi
643 : 334a3: movzbl 0x3(%esi),%eax
644 13825 0.4934 : 334a7: and $0x1f,%eax
645 37 0.0013 : 334aa: or $0x20,%eax
646 34 0.0012 : 334ad: mov %al,0x3(%esi)
647 : src_surf_state->ss0.surface_format = i965_get_card_format(pSrcPicture);
648 28 1.0e-03 : 334b0: mov 0xc(%ebp),%eax
649 : 334b3: call 329b0 <i965_get_card_format>
650 24 8.6e-04 : 334b8: movzwl 0x2(%esi),%edx
651 14209 0.5071 : 334bc: and $0xf803,%dx
652 66 0.0024 : 334c1: and $0x1ff,%ax
653 : 334c5: shl $0x2,%eax
654 3 1.1e-04 : 334c8: or %eax,%edx
656 : src_surf_state->ss0.writedisable_alpha = 0;
657 : src_surf_state->ss0.writedisable_red = 0;
658 : src_surf_state->ss0.writedisable_green = 0;
659 : src_surf_state->ss0.writedisable_blue = 0;
660 : src_surf_state->ss0.color_blend = 1;
661 53 0.0019 : 334ca: movzbl 0x1(%esi),%eax
662 327 0.0117 : 334ce: mov %dx,0x2(%esi)
663 25 8.9e-04 : 334d2: andb $0xfc,0x2(%esi)
664 14928 0.5328 : 334d6: and $0x21,%eax
665 : src_surf_state->ss0.vert_line_stride = 0;
666 : src_surf_state->ss0.vert_line_stride_ofs = 0;
667 : src_surf_state->ss0.mipmap_layout_mode = 0;
668 : src_surf_state->ss0.render_cache_read_mode = 0;
669 1 3.6e-05 : 334d9: or $0x20,%eax
670 : 334dc: mov %al,0x1(%esi)
672 : src_surf_state->ss1.base_addr = src_offset;
673 : 334df: mov 0xffffffa0(%ebp),%eax
674 26 9.3e-04 : 334e2: mov %eax,0x4(%esi)
675 : src_surf_state->ss2.width = pSrc->drawable.width - 1;
676 : 334e5: mov 0x18(%ebp),%ecx
677 : 334e8: mov 0x8(%esi),%eax
678 : 334eb: movzwl 0xc(%ecx),%edx
679 40 0.0014 : 334ef: and $0xfff8003f,%eax
680 : 334f4: sub $0x1,%edx
681 : 334f7: and $0x1fff,%edx
682 : 334fd: shl $0x6,%edx
683 33 0.0012 : 33500: or %edx,%eax
684 54 0.0019 : 33502: mov %eax,0x8(%esi)
685 : src_surf_state->ss2.height = pSrc->drawable.height - 1;
686 9 3.2e-04 : 33505: movzwl 0xe(%ecx),%edx
687 : 33509: movzwl 0xa(%esi),%eax
688 : src_surf_state->ss2.mip_count = 0;
689 : src_surf_state->ss2.render_target_rotation = 0;
690 15025 0.5362 : 3350d: andb $0xc0,0x8(%esi)
691 6407 0.2287 : 33511: sub $0x1,%edx
692 : 33514: shl $0x3,%edx
693 : 33517: and $0x7,%eax
694 : 3351a: or %edx,%eax
695 38 0.0014 : 3351c: mov %ax,0xa(%esi)
696 : src_surf_state->ss3.pitch = src_pitch - 1;
697 : 33520: mov 0xffffffa4(%ebp),%edx
698 : 33523: mov 0xc(%esi),%eax
699 178 0.0064 : 33526: sub $0x1,%edx
700 27 9.6e-04 : 33529: and $0x3ffff,%edx
701 : 3352f: shl $0x3,%edx
702 : 33532: and $0xffe00007,%eax
703 : 33537: or %edx,%eax
704 38 0.0014 : 33539: mov %eax,0xc(%esi)
706 : /* setup mask surface */
708 : 3353c: mov 0x1c(%ebp),%ecx
709 : 3353f: test %ecx,%ecx
710 : 33541: je 338a5 <i965_prepare_composite+0xa15>
711 : memset(mask_surf_state, 0, sizeof(*mask_surf_state));
712 12 4.3e-04 : 33547: mov 0x29d0(%ebx),%eax
713 19 6.8e-04 : 3354d: movl $0x0,(%eax)
714 1 3.6e-05 : 33553: movl $0x0,0x4(%eax)
715 2 7.1e-05 : 3355a: movl $0x0,0x8(%eax)
716 : 33561: movl $0x0,0xc(%eax)
717 14 5.0e-04 : 33568: movl $0x0,0x10(%eax)
718 : mask_surf_state->ss0.surface_type = BRW_SURFACE_2D;
719 2 7.1e-05 : 3356f: mov 0x29d0(%ebx),%esi
720 1 3.6e-05 : 33575: movzbl 0x3(%esi),%eax
721 7000 0.2498 : 33579: and $0x1f,%eax
722 18 6.4e-04 : 3357c: or $0x20,%eax
723 16 5.7e-04 : 3357f: mov %al,0x3(%esi)
724 : mask_surf_state->ss0.surface_format =
725 20 7.1e-04 : 33582: mov 0x10(%ebp),%eax
726 : 33585: call 329b0 <i965_get_card_format>
727 28 1.0e-03 : 3358a: movzwl 0x2(%esi),%edx
728 7436 0.2654 : 3358e: and $0xf803,%dx
729 18 6.4e-04 : 33593: and $0x1ff,%ax
730 : 33597: shl $0x2,%eax
731 : 3359a: or %eax,%edx
732 : i965_get_card_format(pMaskPicture);
734 : mask_surf_state->ss0.writedisable_alpha = 0;
735 : mask_surf_state->ss0.writedisable_red = 0;
736 : mask_surf_state->ss0.writedisable_green = 0;
737 : mask_surf_state->ss0.writedisable_blue = 0;
738 : mask_surf_state->ss0.color_blend = 1;
739 36 0.0013 : 3359c: movzbl 0x1(%esi),%eax
740 117 0.0042 : 335a0: mov %dx,0x2(%esi)
741 25 8.9e-04 : 335a4: andb $0xfc,0x2(%esi)
742 7753 0.2767 : 335a8: and $0x21,%eax
743 : mask_surf_state->ss0.vert_line_stride = 0;
744 : mask_surf_state->ss0.vert_line_stride_ofs = 0;
745 : mask_surf_state->ss0.mipmap_layout_mode = 0;
746 : mask_surf_state->ss0.render_cache_read_mode = 0;
747 : 335ab: or $0x20,%eax
748 : 335ae: mov %al,0x1(%esi)
750 : mask_surf_state->ss1.base_addr = mask_offset;
751 : 335b1: mov 0xffffffa8(%ebp),%eax
752 15 5.4e-04 : 335b4: mov %eax,0x4(%esi)
753 : mask_surf_state->ss2.width = pMask->drawable.width - 1;
754 : 335b7: mov 0x1c(%ebp),%ecx
755 : 335ba: mov 0x8(%esi),%eax
756 : 335bd: movzwl 0xc(%ecx),%edx
757 23 8.2e-04 : 335c1: and $0xfff8003f,%eax
758 : 335c6: sub $0x1,%edx
759 : 335c9: and $0x1fff,%edx
760 2 7.1e-05 : 335cf: shl $0x6,%edx
761 12 4.3e-04 : 335d2: or %edx,%eax
762 : 335d4: mov %eax,0x8(%esi)
763 : mask_surf_state->ss2.height = pMask->drawable.height - 1;
764 : 335d7: movzwl 0xe(%ecx),%edx
765 1 3.6e-05 : 335db: movzwl 0xa(%esi),%eax
766 : mask_surf_state->ss2.mip_count = 0;
767 : mask_surf_state->ss2.render_target_rotation = 0;
768 7624 0.2721 : 335df: andb $0xc0,0x8(%esi)
769 3264 0.1165 : 335e3: sub $0x1,%edx
770 : 335e6: shl $0x3,%edx
771 : 335e9: and $0x7,%eax
772 : 335ec: or %edx,%eax
773 16 5.7e-04 : 335ee: mov %ax,0xa(%esi)
774 : mask_surf_state->ss3.pitch = mask_pitch - 1;
775 : 335f2: mov 0xffffffac(%ebp),%edx
776 : 335f5: mov 0xc(%esi),%eax
777 21 7.5e-04 : 335f8: sub $0x1,%edx
778 20 7.1e-04 : 335fb: and $0x3ffff,%edx
779 16 5.7e-04 : 33601: and $0xffe00007,%eax
780 : 33606: shl $0x3,%edx
781 : 33609: or %edx,%eax
782 14 5.0e-04 : 3360b: mov %eax,0xc(%esi)
785 : /* Set up a binding table for our surfaces. Only the PS will use it */
786 : binding_table[0] = state_base_offset + dest_surf_offset;
787 2 7.1e-05 : 3360e: mov 0x2a58(%ebx),%eax
788 : 33614: mov 0x2a00(%ebx),%ecx
789 : 3361a: mov %eax,%edx
790 12 4.3e-04 : 3361c: add 0x2a08(%ebx),%edx
791 1 3.6e-05 : 33622: mov %edx,(%ecx)
792 : binding_table[1] = state_base_offset + src_surf_offset;
793 2 7.1e-05 : 33624: mov %eax,%edx
794 : 33626: add 0x2a0c(%ebx),%edx
795 19 6.8e-04 : 3362c: mov %edx,0x4(%ecx)
797 : binding_table[2] = state_base_offset + mask_surf_offset;
798 2 7.1e-05 : 3362f: add 0x2a10(%ebx),%eax
799 : 33635: mov %eax,0x8(%ecx)
801 : /* PS kernel use this sampler */
802 : memset(src_sampler_state, 0, sizeof(*src_sampler_state));
803 15 5.4e-04 : 33638: mov 0x29d4(%ebx),%eax
804 36 0.0013 : 3363e: movl $0x0,(%eax)
805 45 0.0016 : 33644: movl $0x0,0x4(%eax)
806 2 7.1e-05 : 3364b: movl $0x0,0x8(%eax)
807 13 4.6e-04 : 33652: movl $0x0,0xc(%eax)
808 : src_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
809 20 7.1e-04 : 33659: mov 0x29d4(%ebx),%edx
810 4 1.4e-04 : 3365f: orb $0x10,0x3(%edx)
811 : switch(pSrcPicture->filter) {
812 12445 0.4441 : 33663: mov 0xc(%ebp),%esi
813 : 33666: mov 0x44(%esi),%eax
814 : 33669: test %eax,%eax
815 : 3366b: je 33683 <i965_prepare_composite+0x7f3>
816 : 3366d: sub $0x1,%eax
817 : 33670: je 34183 <i965_prepare_composite+0x12f3>
818 : case PictFilterNearest:
819 : src_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST;
820 : src_sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
822 : case PictFilterBilinear:
823 : src_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
824 : src_sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
827 : I830FALLBACK("Bad filter 0x%x\n", pSrcPicture->filter);
830 : memset(default_color_state, 0, sizeof(*default_color_state));
831 : default_color_state->color[0] = 0.0; /* R */
832 : default_color_state->color[1] = 0.0; /* G */
833 : default_color_state->color[2] = 0.0; /* B */
834 : default_color_state->color[3] = 0.0; /* A */
836 : src_sampler_state->ss0.default_color_mode = 0; /* GL mode */
838 : if (!pSrcPicture->repeat) {
839 : src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
840 : src_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
841 : src_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP_BORDER;
842 : src_sampler_state->ss2.default_color_pointer =
843 : (state_base_offset + default_color_offset) >> 5;
845 : src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP;
846 : src_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP;
847 : src_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
849 : src_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
852 : memset(mask_sampler_state, 0, sizeof(*mask_sampler_state));
853 : mask_sampler_state->ss0.lod_preclamp = 1; /* GL mode */
854 : switch(pMaskPicture->filter) {
855 : case PictFilterNearest:
856 : mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_NEAREST;
857 : mask_sampler_state->ss0.mag_filter = BRW_MAPFILTER_NEAREST;
859 : case PictFilterBilinear:
860 : mask_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
861 : mask_sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
864 : I830FALLBACK("Bad filter 0x%x\n", pMaskPicture->filter);
867 : if (!pMaskPicture->repeat) {
868 : mask_sampler_state->ss1.r_wrap_mode =
869 : BRW_TEXCOORDMODE_CLAMP_BORDER;
870 : mask_sampler_state->ss1.s_wrap_mode =
871 : BRW_TEXCOORDMODE_CLAMP_BORDER;
872 : mask_sampler_state->ss1.t_wrap_mode =
873 : BRW_TEXCOORDMODE_CLAMP_BORDER;
874 : mask_sampler_state->ss2.default_color_pointer =
875 : (state_base_offset + default_color_offset)>>5;
877 : mask_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_WRAP;
878 : mask_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_WRAP;
879 : mask_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_WRAP;
881 : mask_sampler_state->ss3.chroma_key_enable = 0; /* disable chromakey */
884 : /* Set up the vertex shader to be disabled (passthrough) */
885 : memset(vs_state, 0, sizeof(*vs_state));
886 : vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
887 : vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
888 : vs_state->vs6.vs_enable = 0;
889 : vs_state->vs6.vert_cache_disable = 1;
891 : /* Set up the SF kernel to do coord interp: for each attribute,
892 : * calculate dA/dx and dA/dy. Hand these interpolation coefficients
893 : * back to SF which then hands pixels off to WM.
896 : memcpy(sf_kernel, sf_kernel_static_mask, sizeof (sf_kernel_static));
897 : else if (rotation_program)
898 : memcpy(sf_kernel, sf_kernel_static_rotation,
899 : sizeof (sf_kernel_static_rotation));
901 : memcpy(sf_kernel, sf_kernel_static, sizeof (sf_kernel_static));
903 : memset(sf_state, 0, sizeof(*sf_state));
904 : sf_state->thread0.kernel_start_pointer =
905 : (state_base_offset + sf_kernel_offset) >> 6;
906 : sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
907 : sf_state->sf1.single_program_flow = 1;
908 : sf_state->sf1.binding_table_entry_count = 0;
909 : sf_state->sf1.thread_priority = 0;
910 : sf_state->sf1.floating_point_mode = 0; /* Mesa does this */
911 : sf_state->sf1.illegal_op_exception_enable = 1;
912 : sf_state->sf1.mask_stack_exception_enable = 1;
913 : sf_state->sf1.sw_exception_enable = 1;
914 : sf_state->thread2.per_thread_scratch_space = 0;
915 : /* scratch space is not used in our kernel */
916 : sf_state->thread2.scratch_space_base_pointer = 0;
917 : sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
918 : sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
919 : sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
920 : /* don't smash vertex header, read start from dw8 */
921 : sf_state->thread3.urb_entry_read_offset = 1;
922 : sf_state->thread3.dispatch_grf_start_reg = 3;
923 : sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
924 : sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
925 : sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
926 : sf_state->thread4.stats_enable = 1;
927 : sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
928 : sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
929 : sf_state->sf6.scissor = 0;
930 : sf_state->sf7.trifan_pv = 2;
931 : sf_state->sf6.dest_org_vbias = 0x8;
932 : sf_state->sf6.dest_org_hbias = 0x8;
934 : /* Set up the PS kernel (dispatched by WM) */
936 : if (pMaskPicture->componentAlpha &&
937 : PICT_FORMAT_RGB(pMaskPicture->format)) {
938 : if (i965_blend_op[op].src_alpha)
939 : memcpy(ps_kernel, ps_kernel_static_maskca_srcalpha,
940 : sizeof (ps_kernel_static_maskca_srcalpha));
942 : memcpy(ps_kernel, ps_kernel_static_maskca,
943 : sizeof (ps_kernel_static_maskca));
945 : memcpy(ps_kernel, ps_kernel_static_masknoca,
946 : sizeof (ps_kernel_static_masknoca));
947 : } else if (rotation_program) {
948 : memcpy(ps_kernel, ps_kernel_static_rotation,
949 : sizeof (ps_kernel_static_rotation));
951 : memcpy(ps_kernel, ps_kernel_static_nomask,
952 : sizeof (ps_kernel_static_nomask));
955 : memset(wm_state, 0, sizeof (*wm_state));
956 : wm_state->thread0.kernel_start_pointer =
957 : (state_base_offset + ps_kernel_offset) >> 6;
958 : wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
959 : wm_state->thread1.single_program_flow = 1;
961 : wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
963 : wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
965 : wm_state->thread2.scratch_space_base_pointer = (state_base_offset +
966 : wm_scratch_offset)>>10;
967 : wm_state->thread2.per_thread_scratch_space = 0;
968 : wm_state->thread3.const_urb_entry_read_length = 0;
969 : wm_state->thread3.const_urb_entry_read_offset = 0;
970 : /* Each pair of attributes (src/mask coords) is one URB entry */
972 : wm_state->thread3.urb_entry_read_length = 2;
974 : wm_state->thread3.urb_entry_read_length = 1;
975 : wm_state->thread3.urb_entry_read_offset = 0;
976 : /* wm kernel use urb from 3, see wm_program in compiler module */
977 : wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
979 : wm_state->wm4.stats_enable = 1; /* statistic */
980 : wm_state->wm4.sampler_state_pointer = (state_base_offset +
981 : src_sampler_offset) >> 5;
982 : wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
983 : wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
984 : wm_state->wm5.thread_dispatch_enable = 1;
985 : /* just use 16-pixel dispatch (4 subspans), don't need to change kernel
988 : wm_state->wm5.enable_16_pix = 1;
989 : wm_state->wm5.enable_8_pix = 0;
990 : wm_state->wm5.early_depth_test = 1;
992 : /* Begin the long sequence of commands needed to set up the 3D
997 : OUT_RING(MI_FLUSH |
998 : MI_STATE_INSTRUCTION_CACHE_FLUSH |
999 : BRW_MI_GLOBAL_SNAPSHOT_RESET);
1000 : OUT_RING(MI_NOOP);
1001 : ADVANCE_LP_RING();
1004 : BEGIN_LP_RING(12);
1006 : /* Match Mesa driver setup */
1007 : OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
1009 : OUT_RING(BRW_CS_URB_STATE | 0);
1010 : OUT_RING((0 << 4) | /* URB Entry Allocation Size */
1011 : (0 << 0)); /* Number of URB Entries */
1013 : /* Zero out the two base address registers so all offsets are
1016 : OUT_RING(BRW_STATE_BASE_ADDRESS | 4);
1017 : OUT_RING(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
1018 : OUT_RING(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
1019 : OUT_RING(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
1020 : /* general state max addr, disabled */
1021 : OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
1022 : /* media object state max addr, disabled */
1023 : OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY);
1025 : /* Set system instruction pointer */
1026 : OUT_RING(BRW_STATE_SIP | 0);
1027 : OUT_RING(state_base_offset + sip_kernel_offset);
1028 : OUT_RING(MI_NOOP);
1029 : ADVANCE_LP_RING();
1032 : BEGIN_LP_RING(26);
1033 : /* Pipe control */
1034 : OUT_RING(BRW_PIPE_CONTROL |
1035 : BRW_PIPE_CONTROL_NOWRITE |
1036 : BRW_PIPE_CONTROL_IS_FLUSH |
1038 : OUT_RING(0); /* Destination address */
1039 : OUT_RING(0); /* Immediate data low DW */
1040 : OUT_RING(0); /* Immediate data high DW */
1042 : /* Binding table pointers */
1043 : OUT_RING(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
1044 : OUT_RING(0); /* vs */
1045 : OUT_RING(0); /* gs */
1046 : OUT_RING(0); /* clip */
1047 : OUT_RING(0); /* sf */
1048 : /* Only the PS uses the binding table */
1049 : OUT_RING(state_base_offset + binding_table_offset); /* ps */
1051 : /* The drawing rectangle clipping is always on. Set it to values that
1052 : * shouldn't do any clipping.
1054 : OUT_RING(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
1055 : OUT_RING(0x00000000); /* ymin, xmin */
1056 : OUT_RING(DRAW_YMAX(pDst->drawable.height - 1) |
1057 : DRAW_XMAX(pDst->drawable.width - 1)); /* ymax, xmax */
1058 : OUT_RING(0x00000000); /* yorigin, xorigin */
1060 : /* skip the depth buffer */
1061 : /* skip the polygon stipple */
1062 : /* skip the polygon stipple offset */
1063 : /* skip the line stipple */
1065 : /* Set the pointers to the 3d pipeline state */
1066 : OUT_RING(BRW_3DSTATE_PIPELINED_POINTERS | 5);
1067 : OUT_RING(state_base_offset + vs_offset); /* 32 byte aligned */
1068 : OUT_RING(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
1069 : OUT_RING(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
1070 : OUT_RING(state_base_offset + sf_offset); /* 32 byte aligned */
1071 : OUT_RING(state_base_offset + wm_offset); /* 32 byte aligned */
1072 : OUT_RING(state_base_offset + cc_offset); /* 64 byte aligned */
1075 : OUT_RING(BRW_URB_FENCE |
1078 : UF0_CLIP_REALLOC |
1082 : OUT_RING(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
1083 : ((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
1084 : ((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
1085 : OUT_RING(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
1086 : ((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
1088 : /* Constant buffer state */
1089 : OUT_RING(BRW_CS_URB_STATE | 0);
1090 : OUT_RING(((URB_CS_ENTRY_SIZE - 1) << 4) |
1091 : (URB_CS_ENTRIES << 0));
1092 : ADVANCE_LP_RING();
1095 : int nelem = pMask ? 3: 2;
1096 : BEGIN_LP_RING(pMask?12:10);
1097 : /* Set up the pointer to our vertex buffer */
1098 : OUT_RING(BRW_3DSTATE_VERTEX_BUFFERS | 3);
1099 : OUT_RING((0 << VB0_BUFFER_INDEX_SHIFT) |
1101 : ((4 * 2 * nelem) << VB0_BUFFER_PITCH_SHIFT));
1102 : OUT_RING(state_base_offset + vb_offset);
1104 : OUT_RING(0); // ignore for VERTEXDATA, but still there
1106 : /* Set up our vertex elements, sourced from the single vertex buffer.
1108 : OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));
1109 : /* vertex coordinates */
1110 : OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1112 : (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1113 : (0 << VE0_OFFSET_SHIFT));
1114 : OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1115 : (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1116 : (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
1117 : (BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
1118 : (4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1120 : OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1122 : (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1123 : (8 << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
1124 : OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1125 : (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1126 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
1127 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
1128 : (8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
1131 : OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
1133 : (BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
1134 : (16 << VE0_OFFSET_SHIFT));
1135 : OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
1136 : (BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
1137 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
1138 : (BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
1139 : (10 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
1142 : ADVANCE_LP_RING();
1146 : ErrorF("try to sync to show any errors...");
1151 : 33676: add $0x8c,%esp
1152 : 3367c: xor %eax,%eax
1158 30 0.0011 : 33683: andl $0xfffe3fff,(%edx)
1159 14939 0.5332 : 33689: andb $0xf1,0x2(%edx)
1160 15110 0.5393 : 3368d: mov 0x29dc(%ebx),%eax
1161 : 33693: movl $0x0,(%eax)
1162 1 3.6e-05 : 33699: movl $0x0,0x4(%eax)
1163 : 336a0: movl $0x0,0x8(%eax)
1164 34 0.0012 : 336a7: movl $0x0,0xc(%eax)
1165 : 336ae: mov 0x29dc(%ebx),%edx
1166 : 336b4: xor %eax,%eax
1167 : 336b6: mov %eax,(%edx)
1168 41 0.0015 : 336b8: mov %eax,0x4(%edx)
1169 : 336bb: mov %eax,0x8(%edx)
1170 : 336be: mov %eax,0xc(%edx)
1171 36 0.0013 : 336c1: mov 0x29d4(%ebx),%ecx
1172 33 0.0012 : 336c7: andb $0xdf,0x3(%ecx)
1173 6323 0.2257 : 336cb: mov 0xc(%ebp),%eax
1174 : 336ce: testb $0x1,0x18(%eax)
1175 : 336d2: jne 337d8 <i965_prepare_composite+0x948>
1176 : 336d8: movzbl 0x4(%ecx),%eax
1177 88 0.0031 : 336dc: and $0xfffffff8,%eax
1178 : 336df: or $0x4,%eax
1179 : 336e2: mov %al,0x4(%ecx)
1180 : 336e5: movzwl 0x4(%ecx),%eax
1181 5627 0.2008 : 336e9: and $0xfe3f,%ax
1182 5 1.8e-04 : 336ed: or $0x1,%ah
1183 18 6.4e-04 : 336f0: mov %ax,0x4(%ecx)
1184 17 6.1e-04 : 336f4: movzbl 0x4(%ecx),%eax
1185 4612 0.1646 : 336f8: and $0xffffffc7,%eax
1186 16 5.7e-04 : 336fb: or $0x20,%eax
1187 15 5.4e-04 : 336fe: mov %al,0x4(%ecx)
1188 43 0.0015 : 33701: mov 0x8(%ecx),%eax
1189 168 0.0060 : 33704: mov 0x2a48(%ebx),%edx
1190 : 3370a: add 0x2a58(%ebx),%edx
1191 2 7.1e-05 : 33710: andb $0xfd,0xf(%ecx)
1192 312 0.0111 : 33714: and $0x1f,%eax
1193 : 33717: and $0xffffffe0,%edx
1194 9 3.2e-04 : 3371a: or %edx,%eax
1195 : 3371c: mov %eax,0x8(%ecx)
1196 : 3371f: mov 0x1c(%ebp),%edx
1197 : 33722: test %edx,%edx
1198 : 33724: je 337f5 <i965_prepare_composite+0x965>
1199 13 4.6e-04 : 3372a: mov 0x29d8(%ebx),%eax
1200 19 6.8e-04 : 33730: movl $0x0,(%eax)
1201 2 7.1e-05 : 33736: movl $0x0,0x4(%eax)
1202 : 3373d: movl $0x0,0x8(%eax)
1203 70 0.0025 : 33744: movl $0x0,0xc(%eax)
1204 2 7.1e-05 : 3374b: mov 0x29d8(%ebx),%ecx
1205 3 1.1e-04 : 33751: orb $0x10,0x3(%ecx)
1206 8123 0.2899 : 33755: mov 0x10(%ebp),%edx
1207 : 33758: mov 0x44(%edx),%eax
1208 : 3375b: test %eax,%eax
1209 : 3375d: je 339b7 <i965_prepare_composite+0xb27>
1210 : 33763: sub $0x1,%eax
1211 : 33766: jne 33676 <i965_prepare_composite+0x7e6>
1212 : 3376c: mov (%ecx),%eax
1213 : 3376e: and $0xfffe3fff,%eax
1214 : 33773: or $0x40,%ah
1215 : 33776: mov %eax,(%ecx)
1216 : 33778: movzbl 0x2(%ecx),%eax
1217 : 3377c: and $0xfffffff1,%eax
1218 : 3377f: or $0x2,%eax
1219 : 33782: mov %al,0x2(%ecx)
1220 : 33785: jmp 339c1 <i965_prepare_composite+0xb31>
1221 : 3378a: lea 0x0(%esi),%esi
1222 13 4.6e-04 : 33790: testw $0xfff,0x8(%edx)
1223 13 4.6e-04 : 33796: je 33316 <i965_prepare_composite+0x486>
1224 2 7.1e-05 : 3379c: mov 0x8(%ebp),%eax
1225 : 3379f: shl $0x4,%eax
1226 18 6.4e-04 : 337a2: mov 0xffffb0f8(%ebx,%eax,1),%esi
1227 : 337a9: test %esi,%esi
1228 1 3.6e-05 : 337ab: je 33316 <i965_prepare_composite+0x486>
1229 : 337b1: mov 0x2a64(%ebx),%eax
1230 45 0.0016 : 337b7: cmp $0x3,%eax
1231 : 337ba: je 343eb <i965_prepare_composite+0x155b>
1232 3 1.1e-04 : 337c0: cmp $0x13,%eax
1233 : 337c3: jne 33316 <i965_prepare_composite+0x486>
1234 80 0.0029 : 337c9: movl $0x12,0x2a64(%ebx)
1235 23 8.2e-04 : 337d3: jmp 33316 <i965_prepare_composite+0x486>
1236 33 0.0012 : 337d8: andb $0xf8,0x4(%ecx)
1237 343 0.0122 : 337dc: andw $0xfe3f,0x4(%ecx)
1238 9699 0.3461 : 337e2: andb $0xc7,0x4(%ecx)
1239 8396 0.2996 : 337e6: andb $0xfd,0xf(%ecx)
1240 3 1.1e-04 : 337ea: mov 0x1c(%ebp),%edx
1241 : 337ed: test %edx,%edx
1242 : 337ef: jne 3372a <i965_prepare_composite+0x89a>
1243 20 7.1e-04 : 337f5: mov 0x29e0(%ebx),%eax
1244 71 0.0025 : 337fb: movl $0x0,(%eax)
1245 119 0.0042 : 33801: movl $0x0,0x4(%eax)
1246 27 9.6e-04 : 33808: movl $0x0,0x8(%eax)
1247 28 1.0e-03 : 3380f: movl $0x0,0xc(%eax)
1248 29 0.0010 : 33816: movl $0x0,0x10(%eax)
1249 7 2.5e-04 : 3381d: movl $0x0,0x14(%eax)
1250 44 0.0016 : 33824: movl $0x0,0x18(%eax)
1251 131 0.0047 : 3382b: mov 0x29e0(%ebx),%edx
1252 13 4.6e-04 : 33831: mov 0x10(%edx),%eax
1253 7635 0.2725 : 33834: and $0xfffc07ff,%eax
1254 18 6.4e-04 : 33839: or $0x40,%ah
1255 29 0.0010 : 3383c: mov %eax,0x10(%edx)
1256 40 0.0014 : 3383f: movzbl 0x18(%edx),%eax
1257 3770 0.1345 : 33843: andb $0x7,0x12(%edx)
1258 4124 0.1472 : 33847: and $0xfffffffe,%eax
1259 : 3384a: or $0x2,%eax
1260 : 3384d: mov %al,0x18(%edx)
1261 1 3.6e-05 : 33850: mov 0xffffffb8(%ebp),%eax
1262 12 4.3e-04 : 33853: test %eax,%eax
1263 : 33855: je 343d5 <i965_prepare_composite+0x1545>
1264 : 3385b: lea 0xffffb414(%ebx),%eax
1265 : 33861: mov %eax,0x4(%esp)
1266 : 33865: mov 0x29f4(%ebx),%eax
1267 : 3386b: movl $0x140,0x8(%esp)
1268 : 33873: mov %eax,(%esp)
1269 : 33876: call 7d88 <memcpy@plt>
1270 : 3387b: jmp 33a90 <i965_prepare_composite+0xc00>
1271 : 33880: cmp $0x4,%edi
1272 : 33883: je 341a1 <i965_prepare_composite+0x1311>
1273 : 33889: cmp $0x14,%edi
1274 : 3388c: lea 0x0(%esi),%esi
1275 : 33890: jne 33302 <i965_prepare_composite+0x472>
1276 : 33896: movl $0x11,0x2a60(%ebx)
1277 : 338a0: jmp 33302 <i965_prepare_composite+0x472>
1278 30 0.0011 : 338a5: mov 0x2a58(%ebx),%edx
1279 28 1.0e-03 : 338ab: mov 0x2a00(%ebx),%eax
1280 1 3.6e-05 : 338b1: mov %edx,%ecx
1281 : 338b3: add 0x2a08(%ebx),%ecx
1282 20 7.1e-04 : 338b9: mov %ecx,(%eax)
1283 2 7.1e-05 : 338bb: add 0x2a0c(%ebx),%edx
1284 5 1.8e-04 : 338c1: mov %edx,0x4(%eax)
1285 1 3.6e-05 : 338c4: jmp 33638 <i965_prepare_composite+0x7a8>
1286 : 338c9: lea 0x0(%esi),%esi
1287 21 7.5e-04 : 338d0: mov 0x18(%ebp),%ecx
1288 55 0.0020 : 338d3: movzwl 0xc(%ecx),%eax
1289 11 3.9e-04 : 338d7: push %eax
1290 4 1.4e-04 : 338d8: mov 0xffffff9c(%ebp),%esi
1291 26 9.3e-04 : 338db: fildl (%esp)
1292 42 0.0015 : 338de: fstps 0x264(%esi)
1293 6 2.1e-04 : 338e4: movzwl 0xe(%ecx),%eax
1294 10 3.6e-04 : 338e8: mov %eax,(%esp)
1295 : 338eb: fildl (%esp)
1296 3 1.1e-04 : 338ee: add $0x4,%esp
1297 9 3.2e-04 : 338f1: fstps 0x268(%esi)
1298 6 2.1e-04 : 338f7: mov 0xc(%ebp),%eax
1299 : 338fa: mov 0x40(%eax),%edx
1300 45 0.0016 : 338fd: mov $0xbf800000,%eax
1301 6 2.1e-04 : 33902: movl $0x0,0x278(%esi)
1302 11 3.9e-04 : 3390c: mov %eax,0x26c(%esi)
1303 2 7.1e-05 : 33912: mov %eax,0x270(%esi)
1304 8 2.9e-04 : 33918: test %edx,%edx
1305 3 1.1e-04 : 3391a: mov %edx,0x274(%esi)
1306 8 2.9e-04 : 33920: je 3393c <i965_prepare_composite+0xaac>
1307 : 33922: movswl 0x6(%edx),%eax
1308 : 33926: movswl 0xe(%edx),%edx
1309 : 3392a: cmp $0xffffffff,%eax
1310 : 3392d: je 343b9 <i965_prepare_composite+0x1529>
1311 : 33933: sub $0x1,%eax
1312 : 33936: je 341b0 <i965_prepare_composite+0x1320>
1313 18 6.4e-04 : 3393c: movl $0x2,0x2a04(%ebx)
1314 27 9.6e-04 : 33946: movl $0x0,0x2a1c(%ebx)
1315 2 7.1e-05 : 33950: movl $0x20,0x2a20(%ebx)
1316 3 1.1e-04 : 3395a: movl $0x40,0x2a24(%ebx)
1317 19 6.8e-04 : 33964: movl $0x400,0x2a40(%ebx)
1318 1 3.6e-05 : 3396e: movl $0x8400,0x2a28(%ebx)
1319 5 1.8e-04 : 33978: movl $0x8440,0x2a34(%ebx)
1320 28 1.0e-03 : 33982: movl $0x8580,0x2a38(%ebx)
1321 32 0.0011 : 3398c: movl $0x89e0,0x2a4c(%ebx)
1322 14 5.0e-04 : 33996: movl $0x8580,0xffffffc0(%ebp)
1323 17 6.1e-04 : 3399d: movl $0x0,0xffffffb8(%ebp)
1324 21 7.5e-04 : 339a4: movl $0x0,0xffffffa8(%ebp)
1325 5 1.8e-04 : 339ab: movl $0x0,0xffffffac(%ebp)
1326 10 3.6e-04 : 339b2: jmp 3301a <i965_prepare_composite+0x18a>
1327 22 7.9e-04 : 339b7: andl $0xfffe3fff,(%ecx)
1328 7801 0.2784 : 339bd: andb $0xf1,0x2(%ecx)
1329 7750 0.2766 : 339c1: mov 0x10(%ebp),%esi
1330 : 339c4: testb $0x1,0x18(%esi)
1331 : 339c8: jne 34170 <i965_prepare_composite+0x12e0>
1332 : 339ce: movzbl 0x4(%ecx),%eax
1333 85 0.0030 : 339d2: and $0xfffffff8,%eax
1334 : 339d5: or $0x4,%eax
1335 : 339d8: mov %al,0x4(%ecx)
1336 : 339db: movzwl 0x4(%ecx),%eax
1337 7606 0.2714 : 339df: and $0xfe3f,%ax
1338 17 6.1e-04 : 339e3: or $0x1,%ah
1339 45 0.0016 : 339e6: mov %ax,0x4(%ecx)
1340 35 0.0012 : 339ea: movzbl 0x4(%ecx),%eax
1341 6070 0.2166 : 339ee: and $0xffffffc7,%eax
1342 16 5.7e-04 : 339f1: or $0x20,%eax
1343 21 7.5e-04 : 339f4: mov %al,0x4(%ecx)
1344 10 3.6e-04 : 339f7: mov 0x8(%ecx),%eax
1345 : 339fa: mov 0x2a48(%ebx),%edx
1346 : 33a00: add 0x2a58(%ebx),%edx
1347 8 2.9e-04 : 33a06: and $0x1f,%eax
1348 10 3.6e-04 : 33a09: and $0xffffffe0,%edx
1349 : 33a0c: or %edx,%eax
1350 3 1.1e-04 : 33a0e: mov %eax,0x8(%ecx)
1351 : 33a11: andb $0xfd,0xf(%ecx)
1352 161 0.0057 : 33a15: mov 0x29e0(%ebx),%eax
1353 2 7.1e-05 : 33a1b: movl $0x0,(%eax)
1354 : 33a21: movl $0x0,0x4(%eax)
1355 30 0.0011 : 33a28: movl $0x0,0x8(%eax)
1356 11 3.9e-04 : 33a2f: movl $0x0,0xc(%eax)
1357 8 2.9e-04 : 33a36: movl $0x0,0x10(%eax)
1358 9 3.2e-04 : 33a3d: movl $0x0,0x14(%eax)
1359 53 0.0019 : 33a44: movl $0x0,0x18(%eax)
1360 65 0.0023 : 33a4b: mov 0x29e0(%ebx),%edx
1361 7 2.5e-04 : 33a51: mov 0x10(%edx),%eax
1362 7749 0.2766 : 33a54: and $0xfffc07ff,%eax
1363 20 7.1e-04 : 33a59: or $0x40,%ah
1364 30 0.0011 : 33a5c: mov %eax,0x10(%edx)
1365 24 8.6e-04 : 33a5f: movzbl 0x18(%edx),%eax
1366 2954 0.1054 : 33a63: andb $0x7,0x12(%edx)
1367 4359 0.1556 : 33a67: and $0xfffffffe,%eax
1368 : 33a6a: or $0x2,%eax
1369 : 33a6d: mov %al,0x18(%edx)
1370 1 3.6e-05 : 33a70: lea 0xffffb274(%ebx),%eax
1371 47 0.0017 : 33a76: mov %eax,0x4(%esp)
1372 22 7.9e-04 : 33a7a: mov 0x29f4(%ebx),%eax
1373 : 33a80: movl $0x110,0x8(%esp)
1374 229 0.0082 : 33a88: mov %eax,(%esp)
1375 4 1.4e-04 : 33a8b: call 7d88 <memcpy@plt>
1376 49 0.0017 : 33a90: mov 0x29e4(%ebx),%edi
1377 : 33a96: xor %eax,%eax
1378 : 33a98: mov $0x8,%ecx
1380 509 0.0182 : 33a9e: rep stos %eax,%es:(%edi)
1381 235 0.0084 : 33aa0: mov 0x29e4(%ebx),%eax
1382 31 0.0011 : 33aa6: mov 0x2a34(%ebx),%ecx
1383 21 7.5e-04 : 33aac: add 0x2a58(%ebx),%ecx
1384 60 0.0021 : 33ab2: mov (%eax),%edx
1385 19787 0.7062 : 33ab4: and $0xffffffc0,%ecx
1386 : 33ab7: andb $0x81,0xf(%eax)
1387 13800 0.4925 : 33abb: andb $0x3,0xe(%eax)
1388 7250 0.2587 : 33abf: and $0x3f,%edx
1389 27 9.6e-04 : 33ac2: or %ecx,%edx
1390 7 2.5e-04 : 33ac4: mov %edx,(%eax)
1391 1 3.6e-05 : 33ac6: mov 0xc(%eax),%edx
1392 16615 0.5930 : 33ac9: orb $0x80,0x7(%eax)
1393 6135 0.2189 : 33acd: andw $0xfc03,0x6(%eax)
1394 31133 1.1111 : 33ad3: andb $0xf0,0x8(%eax)
1395 958 0.0342 : 33ad7: and $0xfffe07ff,%edx
1396 : 33add: or $0x8,%dh
1397 29 0.0010 : 33ae0: mov %edx,0xc(%eax)
1398 2 7.1e-05 : 33ae3: movzwl 0xc(%eax),%edx
1399 14701 0.5247 : 33ae7: andb $0xf1,(%eax)
1400 1449 0.0517 : 33aea: andb $0xfc,0x6(%eax)
1401 12439 0.4439 : 33aee: orb $0x28,0x5(%eax)
1402 2268 0.0809 : 33af2: and $0xfc0f,%dx
1403 : 33af7: or $0x10,%edx
1404 22 7.9e-04 : 33afa: mov %dx,0xc(%eax)
1405 10 3.6e-04 : 33afe: movzbl 0xc(%eax),%edx
1406 14092 0.5029 : 33b02: orb $0x80,0x4(%eax)
1407 40 0.0014 : 33b06: andl $0x3ff,0x8(%eax)
1408 2795 0.0997 : 33b0d: and $0xfffffff0,%edx
1409 : 33b10: or $0x3,%edx
1410 14 5.0e-04 : 33b13: mov %dl,0xc(%eax)
1411 20 7.1e-04 : 33b16: andb $0x81,0x13(%eax)
1412 898 0.0320 : 33b1a: movzbl 0x12(%eax),%edx
1413 1120 0.0400 : 33b1e: andb $0xfd,0x1a(%eax)
1414 978 0.0349 : 33b22: andb $0xfd,0x14(%eax)
1415 347 0.0124 : 33b26: and $0x7,%edx
1416 : 33b29: or $0x8,%edx
1417 20 7.1e-04 : 33b2c: mov %dl,0x12(%eax)
1418 7 2.5e-04 : 33b2f: mov 0x10(%eax),%edx
1419 16298 0.5817 : 33b32: and $0xfffc07ff,%edx
1420 25 8.9e-04 : 33b38: or $0x8,%dh
1421 65 0.0023 : 33b3b: mov %edx,0x10(%eax)
1422 54 0.0019 : 33b3e: movzbl 0x1b(%eax),%edx
1423 324 0.0116 : 33b42: orb $0x4,0x11(%eax)
1424 13376 0.4774 : 33b46: and $0xffffff9f,%edx
1425 : 33b49: or $0x20,%edx
1426 : 33b4c: mov %dl,0x1b(%eax)
1427 : 33b4f: movzbl 0x1f(%eax),%edx
1428 38 0.0014 : 33b53: and $0xfffffff9,%edx
1429 : 33b56: or $0x4,%edx
1430 : 33b59: mov %dl,0x1f(%eax)
1431 1 3.6e-05 : 33b5c: movzbl 0x19(%eax),%edx
1432 139 0.0050 : 33b60: and $0xffffffe1,%edx
1433 : 33b63: or $0x10,%edx
1434 : 33b66: mov %dl,0x19(%eax)
1435 2 7.1e-05 : 33b69: mov 0x18(%eax),%edx
1436 11186 0.3992 : 33b6c: and $0xfffe1fff,%edx
1437 36 0.0013 : 33b72: or $0x10000,%edx
1438 42 0.0015 : 33b78: mov %edx,0x18(%eax)
1439 22 7.9e-04 : 33b7b: mov 0x1c(%ebp),%eax
1440 : 33b7e: test %eax,%eax
1441 : 33b80: je 342e5 <i965_prepare_composite+0x1455>
1442 11 3.9e-04 : 33b86: mov 0x10(%ebp),%eax
1443 1 3.6e-05 : 33b89: testb $0x1,0x19(%eax)
1444 8 2.9e-04 : 33b8d: je 34234 <i965_prepare_composite+0x13a4>
1445 4 1.4e-04 : 33b93: testw $0xfff,0x8(%eax)
1446 2 7.1e-05 : 33b99: je 34234 <i965_prepare_composite+0x13a4>
1447 : 33b9f: shll $0x4,0x8(%ebp)
1448 22 7.9e-04 : 33ba3: mov 0x8(%ebp),%edx
1449 1 3.6e-05 : 33ba6: mov 0xffffb0f8(%ebx,%edx,1),%eax
1450 15 5.4e-04 : 33bad: test %eax,%eax
1451 : 33baf: je 343c7 <i965_prepare_composite+0x1537>
1452 7 2.5e-04 : 33bb5: lea 0xffffb674(%ebx),%eax
1453 18 6.4e-04 : 33bbb: nop
1454 : 33bbc: lea 0x0(%esi),%esi
1455 19 6.8e-04 : 33bc0: mov %eax,0x4(%esp)
1456 75 0.0027 : 33bc4: mov 0x29f8(%ebx),%eax
1457 : 33bca: movl $0x5f0,0x8(%esp)
1458 9 3.2e-04 : 33bd2: mov %eax,(%esp)
1459 20 7.1e-04 : 33bd5: call 7d88 <memcpy@plt>
1460 24 8.6e-04 : 33bda: mov 0x29e8(%ebx),%edi
1461 : 33be0: xor %eax,%eax
1462 : 33be2: mov $0x8,%ecx
1464 284 0.0101 : 33be8: rep stos %eax,%es:(%edi)
1465 149 0.0053 : 33bea: mov 0x29e8(%ebx),%ecx
1466 19 6.8e-04 : 33bf0: mov 0x2a58(%ebx),%esi
1467 10 3.6e-04 : 33bf6: mov (%ecx),%eax
1468 10010 0.3572 : 33bf8: mov %esi,%edx
1469 : 33bfa: add 0x2a38(%ebx),%edx
1470 : 33c00: orb $0x80,0x7(%ecx)
1471 5995 0.2140 : 33c04: and $0x3f,%eax
1472 : 33c07: and $0xffffffc0,%edx
1473 : 33c0a: or %edx,%eax
1474 : 33c0c: mov %esi,%edx
1475 21 7.5e-04 : 33c0e: mov %eax,(%ecx)
1476 : 33c10: movzbl (%ecx),%eax
1477 7306 0.2607 : 33c13: and $0xfffffff1,%eax
1478 14 5.0e-04 : 33c16: or $0x2,%eax
1479 17 6.1e-04 : 33c19: mov %al,(%ecx)
1480 20 7.1e-04 : 33c1b: movzwl 0x6(%ecx),%eax
1481 4771 0.1703 : 33c1f: and $0xfc03,%ax
1482 25 8.9e-04 : 33c23: or $0xc,%eax
1483 27 9.6e-04 : 33c26: mov %ax,0x6(%ecx)
1484 22 7.9e-04 : 33c2a: mov 0x8(%ecx),%eax
1485 737 0.0263 : 33c2d: add 0x2a40(%ebx),%edx
1486 : 33c33: andb $0x81,0xf(%ecx)
1487 3387 0.1209 : 33c37: andb $0x3,0xe(%ecx)
1488 4057 0.1448 : 33c3b: and $0xfffffc00,%edx
1489 5 1.8e-04 : 33c41: and $0x3ff,%eax
1490 5 1.8e-04 : 33c46: or %edx,%eax
1491 : 33c48: mov %eax,0x8(%ecx)
1492 13 4.6e-04 : 33c4b: mov 0xc(%ecx),%eax
1493 7489 0.2673 : 33c4e: andb $0xf0,0x8(%ecx)
1494 2944 0.1051 : 33c52: and $0xfffe07ff,%eax
1495 : 33c57: or $0x10,%ah
1496 1 3.6e-05 : 33c5a: mov %eax,0xc(%ecx)
1497 30 0.0011 : 33c5d: andw $0xfc0f,0xc(%ecx)
1498 13013 0.4644 : 33c63: movzbl 0xc(%ecx),%eax
1499 12997 0.4638 : 33c67: orb $0x1,0x10(%ecx)
1500 2 7.1e-05 : 33c6b: movzbl 0x16(%ecx),%edx
1501 3 1.1e-04 : 33c6f: and $0xfffffff0,%eax
1502 36 0.0013 : 33c72: or $0x3,%eax
1503 28 1.0e-03 : 33c75: mov %al,0xc(%ecx)
1504 39 0.0014 : 33c78: mov 0x10(%ecx),%eax
1505 10942 0.3905 : 33c7b: or $0xc,%edx
1506 : 33c7e: add 0x2a14(%ebx),%esi
1507 27 9.6e-04 : 33c84: mov %dl,0x16(%ecx)
1508 1 3.6e-05 : 33c87: and $0xffffffe0,%esi
1509 12 4.3e-04 : 33c8a: and $0x1f,%eax
1510 14 5.0e-04 : 33c8d: or %esi,%eax
1511 13 4.6e-04 : 33c8f: mov %eax,0x10(%ecx)
1512 47 0.0017 : 33c92: movzbl 0x10(%ecx),%eax
1513 10716 0.3824 : 33c96: and $0xffffffe3,%eax
1514 27 9.6e-04 : 33c99: or $0x4,%eax
1515 39 0.0014 : 33c9c: mov %al,0x10(%ecx)
1516 39 0.0014 : 33c9f: movzbl 0x17(%ecx),%eax
1517 1 3.6e-05 : 33ca3: and $0xffffff81,%eax
1518 : 33ca6: or $0x3e,%eax
1519 : 33ca9: mov %al,0x17(%ecx)
1520 34 0.0012 : 33cac: movzbl 0x14(%ecx),%eax
1521 59 0.0021 : 33cb0: or $0x2,%eax
1522 : 33cb3: and $0xfffffffe,%eax
1523 : 33cb6: mov %al,0x14(%ecx)
1524 33 0.0012 : 33cb9: mov 0xffffff9c(%ebp),%ecx
1525 : 33cbc: mov 0x6c(%ecx),%edx
1526 : 33cbf: cmpl $0x7,0x14(%edx)
1527 50 0.0018 : 33cc3: jle 34251 <i965_prepare_composite+0x13c1>
1528 25 8.9e-04 : 33cc9: mov 0x10(%edx),%eax
1529 1 3.6e-05 : 33ccc: mov 0x8(%edx),%ecx
1530 2 7.1e-05 : 33ccf: mov (%edx),%esi
1531 : 33cd1: lea (%ecx,%eax,1),%edx
1532 21 7.5e-04 : 33cd4: add $0x4,%eax
1533 : 33cd7: and %esi,%eax
1534 2 7.1e-05 : 33cd9: add %eax,%ecx
1535 : 33cdb: movl $0x200000a,(%edx)
1536 35 0.0012 : 33ce1: lea 0x4(%eax),%edx
1537 : 33ce4: movl $0x0,(%ecx)
1538 20 7.1e-04 : 33cea: mov 0xffffff9c(%ebp),%ecx
1539 2 7.1e-05 : 33ced: and %esi,%edx
1540 33 0.0012 : 33cef: mov 0x6c(%ecx),%eax
1541 2 7.1e-05 : 33cf2: mov %edx,0x10(%eax)
1542 7 2.5e-04 : 33cf5: mov 0x6c(%ecx),%eax
1543 6 2.1e-04 : 33cf8: subl $0x8,0x14(%eax)
1544 38 0.0014 : 33cfc: test $0x7,%dl
1545 2 7.1e-05 : 33cff: jne 343fa <i965_prepare_composite+0x156a>
1546 78 0.0028 : 33d05: mov 0xffffff9c(%ebp),%esi
1547 12 4.3e-04 : 33d08: mov (%esi),%eax
1548 41 0.0015 : 33d0a: mov %edx,0x2030(%eax)
1549 4758 0.1698 : 33d10: mov 0x6c(%esi),%edx
1550 106 0.0038 : 33d13: cmpl $0x2f,0x14(%edx)
1551 117 0.0042 : 33d17: jle 34277 <i965_prepare_composite+0x13e7>
1552 32 0.0011 : 33d1d: mov 0x8(%edx),%ecx
1553 4 1.4e-04 : 33d20: mov 0x10(%edx),%eax
1554 : 33d23: mov (%edx),%esi
1555 20 7.1e-04 : 33d25: lea (%ecx,%eax,1),%edx
1556 3 1.1e-04 : 33d28: add $0x4,%eax
1557 11 3.9e-04 : 33d2b: and %esi,%eax
1558 23 8.2e-04 : 33d2d: movl $0x61040000,(%edx)
1559 126 0.0045 : 33d33: lea (%ecx,%eax,1),%edx
1560 : 33d36: add $0x4,%eax
1561 4 1.4e-04 : 33d39: and %esi,%eax
1562 : 33d3b: movl $0x60010000,(%edx)
1563 122 0.0044 : 33d41: lea (%ecx,%eax,1),%edx
1564 : 33d44: add $0x4,%eax
1565 4 1.4e-04 : 33d47: and %esi,%eax
1566 10 3.6e-04 : 33d49: movl $0x0,(%edx)
1567 65 0.0023 : 33d4f: lea (%ecx,%eax,1),%edx
1568 : 33d52: add $0x4,%eax
1569 1 3.6e-05 : 33d55: and %esi,%eax
1570 5 1.8e-04 : 33d57: movl $0x61010004,(%edx)
1571 77 0.0027 : 33d5d: lea (%ecx,%eax,1),%edx
1572 : 33d60: add $0x4,%eax
1573 : 33d63: and %esi,%eax
1574 2 7.1e-05 : 33d65: movl $0x1,(%edx)
1575 60 0.0021 : 33d6b: lea (%ecx,%eax,1),%edx
1576 : 33d6e: add $0x4,%eax
1577 3 1.1e-04 : 33d71: and %esi,%eax
1578 5 1.8e-04 : 33d73: movl $0x1,(%edx)
1579 85 0.0030 : 33d79: lea (%ecx,%eax,1),%edx
1580 : 33d7c: add $0x4,%eax
1581 1 3.6e-05 : 33d7f: and %esi,%eax
1582 81 0.0029 : 33d81: movl $0x1,(%edx)
1583 56 0.0020 : 33d87: lea (%ecx,%eax,1),%edx
1584 : 33d8a: add $0x4,%eax
1585 5 1.8e-04 : 33d8d: and %esi,%eax
1586 1 3.6e-05 : 33d8f: movl $0x10000001,(%edx)
1587 58 0.0021 : 33d95: lea (%ecx,%eax,1),%edx
1588 : 33d98: add $0x4,%eax
1589 1 3.6e-05 : 33d9b: and %esi,%eax
1590 1 3.6e-05 : 33d9d: movl $0x10000001,(%edx)
1591 72 0.0026 : 33da3: lea (%ecx,%eax,1),%edx
1592 : 33da6: add $0x4,%eax
1593 2 7.1e-05 : 33da9: movl $0x61020000,(%edx)
1594 85 0.0030 : 33daf: and %esi,%eax
1595 : 33db1: mov 0x2a3c(%ebx),%edx
1596 91 0.0032 : 33db7: add 0x2a58(%ebx),%edx
1597 95 0.0034 : 33dbd: lea (%ecx,%eax,1),%edi
1598 1 3.6e-05 : 33dc0: add $0x4,%eax
1599 9 3.2e-04 : 33dc3: and %esi,%eax
1600 : 33dc5: add %eax,%ecx
1601 27 9.6e-04 : 33dc7: mov %edx,(%edi)
1602 12 4.3e-04 : 33dc9: lea 0x4(%eax),%edx
1603 : 33dcc: movl $0x0,(%ecx)
1604 56 0.0020 : 33dd2: mov 0xffffff9c(%ebp),%ecx
1605 125 0.0045 : 33dd5: and %esi,%edx
1606 : 33dd7: mov 0x6c(%ecx),%eax
1607 147 0.0052 : 33dda: mov %edx,0x10(%eax)
1608 130 0.0046 : 33ddd: mov 0x6c(%ecx),%eax
1609 122 0.0044 : 33de0: subl $0x30,0x14(%eax)
1610 583 0.0208 : 33de4: test $0x7,%dl
1611 : 33de7: jne 343fa <i965_prepare_composite+0x156a>
1612 4 1.4e-04 : 33ded: mov 0xffffff9c(%ebp),%esi
1613 202 0.0072 : 33df0: mov (%esi),%eax
1614 194 0.0069 : 33df2: mov %edx,0x2030(%eax)
1615 16218 0.5788 : 33df8: mov 0x6c(%esi),%edx
1616 172 0.0061 : 33dfb: cmpl $0x67,0x14(%edx)
1617 133 0.0047 : 33dff: jle 342a0 <i965_prepare_composite+0x1410>
1618 122 0.0044 : 33e05: mov (%edx),%ecx
1619 9 3.2e-04 : 33e07: mov 0x10(%edx),%eax
1620 4 1.4e-04 : 33e0a: mov %ecx,0xffffffd8(%ebp)
1621 18 6.4e-04 : 33e0d: mov 0x8(%edx),%edi
1622 14 5.0e-04 : 33e10: lea (%edi,%eax,1),%edx
1623 32 0.0011 : 33e13: add $0x4,%eax
1624 : 33e16: and %ecx,%eax
1625 7 2.5e-04 : 33e18: movl $0x7a000802,(%edx)
1626 179 0.0064 : 33e1e: lea (%edi,%eax,1),%edx
1627 2 7.1e-05 : 33e21: add $0x4,%eax
1628 : 33e24: and %ecx,%eax
1629 : 33e26: movl $0x0,(%edx)
1630 54 0.0019 : 33e2c: lea (%edi,%eax,1),%edx
1631 5 1.8e-04 : 33e2f: add $0x4,%eax
1632 : 33e32: and %ecx,%eax
1633 3 1.1e-04 : 33e34: movl $0x0,(%edx)
1634 68 0.0024 : 33e3a: lea (%edi,%eax,1),%edx
1635 1 3.6e-05 : 33e3d: add $0x4,%eax
1636 : 33e40: and %ecx,%eax
1637 58 0.0021 : 33e42: movl $0x0,(%edx)
1638 76 0.0027 : 33e48: lea (%edi,%eax,1),%edx
1639 : 33e4b: add $0x4,%eax
1640 : 33e4e: and %ecx,%eax
1641 1 3.6e-05 : 33e50: movl $0x78010004,(%edx)
1642 54 0.0019 : 33e56: lea (%edi,%eax,1),%edx
1643 2 7.1e-05 : 33e59: add $0x4,%eax
1644 : 33e5c: and %ecx,%eax
1645 4 1.4e-04 : 33e5e: movl $0x0,(%edx)
1646 88 0.0031 : 33e64: lea (%edi,%eax,1),%edx
1647 1 3.6e-05 : 33e67: add $0x4,%eax
1648 : 33e6a: and %ecx,%eax
1649 1 3.6e-05 : 33e6c: movl $0x0,(%edx)
1650 56 0.0020 : 33e72: lea (%edi,%eax,1),%edx
1651 1 3.6e-05 : 33e75: add $0x4,%eax
1652 : 33e78: and %ecx,%eax
1653 : 33e7a: movl $0x0,(%edx)
1654 73 0.0026 : 33e80: lea (%edi,%eax,1),%edx
1655 9 3.2e-04 : 33e83: add $0x4,%eax
1656 : 33e86: movl $0x0,(%edx)
1657 67 0.0024 : 33e8c: mov 0x2a58(%ebx),%esi
1658 78 0.0028 : 33e92: and %ecx,%eax
1659 2 7.1e-05 : 33e94: lea (%edi,%eax,1),%ecx
1660 : 33e97: add $0x4,%eax
1661 28 1.0e-03 : 33e9a: mov %esi,%edx
1662 6 2.1e-04 : 33e9c: add 0x2a44(%ebx),%edx
1663 58 0.0021 : 33ea2: mov %edx,(%ecx)
1664 39 0.0014 : 33ea4: and 0xffffffd8(%ebp),%eax
1665 92 0.0033 : 33ea7: lea (%edi,%eax,1),%edx
1666 24 8.6e-04 : 33eaa: add $0x4,%eax
1667 6 2.1e-04 : 33ead: movl $0x79000002,(%edx)
1668 160 0.0057 : 33eb3: and 0xffffffd8(%ebp),%eax
1669 13 4.6e-04 : 33eb6: lea (%edi,%eax,1),%edx
1670 25 8.9e-04 : 33eb9: add $0x4,%eax
1671 6 2.1e-04 : 33ebc: movl $0x0,(%edx)
1672 206 0.0074 : 33ec2: mov 0x20(%ebp),%ecx
1673 112 0.0040 : 33ec5: and 0xffffffd8(%ebp),%eax
1674 39 0.0014 : 33ec8: lea (%edi,%eax,1),%edx
1675 25 8.9e-04 : 33ecb: add $0x4,%eax
1676 5 1.8e-04 : 33ece: mov %edx,0xffffffdc(%ebp)
1677 21 7.5e-04 : 33ed1: movzwl 0xe(%ecx),%edx
1678 80 0.0029 : 33ed5: movzwl 0xc(%ecx),%ecx
1679 14 5.0e-04 : 33ed9: sub $0x1,%edx
1680 3 1.1e-04 : 33edc: mov %ecx,0xffffff84(%ebp)
1681 35 0.0012 : 33edf: shl $0x10,%edx
1682 4 1.4e-04 : 33ee2: sub $0x1,%ecx
1683 12 4.3e-04 : 33ee5: or %ecx,%edx
1684 27 9.6e-04 : 33ee7: mov 0xffffffdc(%ebp),%ecx
1685 24 8.6e-04 : 33eea: mov %edx,(%ecx)
1686 145 0.0052 : 33eec: and 0xffffffd8(%ebp),%eax
1687 230 0.0082 : 33eef: lea (%edi,%eax,1),%edx
1688 39 0.0014 : 33ef2: add $0x4,%eax
1689 12 4.3e-04 : 33ef5: movl $0x0,(%edx)
1690 182 0.0065 : 33efb: and 0xffffffd8(%ebp),%eax
1691 4 1.4e-04 : 33efe: lea (%edi,%eax,1),%edx
1692 118 0.0042 : 33f01: add $0x4,%eax
1693 3 1.1e-04 : 33f04: movl $0x78000005,(%edx)
1694 175 0.0062 : 33f0a: mov %esi,%edx
1695 7 2.5e-04 : 33f0c: and 0xffffffd8(%ebp),%eax
1696 11 3.9e-04 : 33f0f: add 0x2a1c(%ebx),%edx
1697 154 0.0055 : 33f15: lea (%edi,%eax,1),%ecx
1698 3 1.1e-04 : 33f18: add $0x4,%eax
1699 17 6.1e-04 : 33f1b: mov %edx,(%ecx)
1700 169 0.0060 : 33f1d: and 0xffffffd8(%ebp),%eax
1701 : 33f20: lea (%edi,%eax,1),%edx
1702 24 8.6e-04 : 33f23: add $0x4,%eax
1703 3 1.1e-04 : 33f26: movl $0x0,(%edx)
1704 154 0.0055 : 33f2c: and 0xffffffd8(%ebp),%eax
1705 563 0.0201 : 33f2f: lea (%edi,%eax,1),%edx
1706 728 0.0260 : 33f32: add $0x4,%eax
1707 1721 0.0614 : 33f35: movl $0x0,(%edx)
1708 4024 0.1436 : 33f3b: mov %esi,%edx
1709 : 33f3d: and 0xffffffd8(%ebp),%eax
1710 173 0.0062 : 33f40: add 0x2a20(%ebx),%edx
1711 36 0.0013 : 33f46: lea (%edi,%eax,1),%ecx
1712 11 3.9e-04 : 33f49: add $0x4,%eax
1713 13 4.6e-04 : 33f4c: mov %edx,(%ecx)
1714 168 0.0060 : 33f4e: mov %esi,%edx
1715 : 33f50: and 0xffffffd8(%ebp),%eax
1716 7 2.5e-04 : 33f53: add 0x2a24(%ebx),%edx
1717 25 8.9e-04 : 33f59: lea (%edi,%eax,1),%ecx
1718 28 1.0e-03 : 33f5c: add $0x4,%eax
1719 19 6.8e-04 : 33f5f: mov %edx,(%ecx)
1720 176 0.0063 : 33f61: and 0xffffffd8(%ebp),%eax
1721 : 33f64: add 0x2a28(%ebx),%esi
1722 25 8.9e-04 : 33f6a: lea (%edi,%eax,1),%edx
1723 1 3.6e-05 : 33f6d: add $0x4,%eax
1724 18 6.4e-04 : 33f70: mov %esi,(%edx)
1725 180 0.0064 : 33f72: and 0xffffffd8(%ebp),%eax
1726 1 3.6e-05 : 33f75: lea (%edi,%eax,1),%edx
1727 28 1.0e-03 : 33f78: add $0x4,%eax
1728 2 7.1e-05 : 33f7b: movl $0x60002f01,(%edx)
1729 214 0.0076 : 33f81: mov 0x29b4(%ebx),%edx
1730 : 33f87: and 0xffffffd8(%ebp),%eax
1731 30 0.0011 : 33f8a: add 0x29b0(%ebx),%edx
1732 37 0.0013 : 33f90: mov 0x29a4(%ebx),%ecx
1733 : 33f96: lea (%edi,%eax,1),%esi
1734 2 7.1e-05 : 33f99: add $0x4,%eax
1735 10 3.6e-04 : 33f9c: mov %esi,0xffffffe0(%ebp)
1736 20 7.1e-04 : 33f9f: mov 0x29ac(%ebx),%esi
1737 : 33fa5: shl $0x14,%edx
1738 2 7.1e-05 : 33fa8: add 0x29a0(%ebx),%ecx
1739 57 0.0020 : 33fae: add 0x29a8(%ebx),%esi
1740 36 0.0013 : 33fb4: or %ecx,%edx
1741 21 7.5e-04 : 33fb6: shl $0xa,%esi
1742 12 4.3e-04 : 33fb9: or %edx,%esi
1743 32 0.0011 : 33fbb: mov 0xffffffe0(%ebp),%edx
1744 3 1.1e-04 : 33fbe: mov %esi,(%edx)
1745 133 0.0047 : 33fc0: mov 0x29c4(%ebx),%edx
1746 118 0.0042 : 33fc6: add 0x29c0(%ebx),%edx
1747 15 5.4e-04 : 33fcc: mov 0x29bc(%ebx),%ecx
1748 5 1.8e-04 : 33fd2: add 0x29b8(%ebx),%ecx
1749 46 0.0016 : 33fd8: and 0xffffffd8(%ebp),%eax
1750 18 6.4e-04 : 33fdb: shl $0x14,%edx
1751 19 6.8e-04 : 33fde: or %ecx,%edx
1752 15 5.4e-04 : 33fe0: lea (%edi,%eax,1),%esi
1753 9 3.2e-04 : 33fe3: add $0x4,%eax
1754 2 7.1e-05 : 33fe6: mov %edx,(%esi)
1755 132 0.0047 : 33fe8: and 0xffffffd8(%ebp),%eax
1756 1 3.6e-05 : 33feb: lea (%edi,%eax,1),%edx
1757 14 5.0e-04 : 33fee: add $0x4,%eax
1758 3 1.1e-04 : 33ff1: movl $0x60010000,(%edx)
1759 162 0.0058 : 33ff7: and 0xffffffd8(%ebp),%eax
1760 1 3.6e-05 : 33ffa: add %eax,%edi
1761 27 9.6e-04 : 33ffc: movl $0xfffffff0,(%edi)
1762 271 0.0097 : 34002: mov 0xffffff9c(%ebp),%ecx
1763 3 1.1e-04 : 34005: lea 0x4(%eax),%edx
1764 : 34008: and 0xffffffd8(%ebp),%edx
1765 21 7.5e-04 : 3400b: mov 0x6c(%ecx),%eax
1766 44 0.0016 : 3400e: mov %edx,0x10(%eax)
1767 167 0.0060 : 34011: mov 0x6c(%ecx),%eax
1768 154 0.0055 : 34014: subl $0x68,0x14(%eax)
1769 213 0.0076 : 34018: test $0x7,%dl
1770 : 3401b: jne 343fa <i965_prepare_composite+0x156a>
1771 : 34021: mov 0xffffff9c(%ebp),%esi
1772 202 0.0072 : 34024: mov (%esi),%eax
1773 62 0.0022 : 34026: mov %edx,0x2030(%eax)
1774 10060 0.3590 : 3402c: mov 0x1c(%ebp),%eax
1775 4 1.4e-04 : 3402f: test %eax,%eax
1776 : 34031: je 34398 <i965_prepare_composite+0x1508>
1777 : 34037: movl $0x30,0xffffffbc(%ebp)
1778 2 7.1e-05 : 3403e: movl $0x18,0xffffffc4(%ebp)
1779 17 6.1e-04 : 34045: movl $0x78090005,0xffffffc8(%ebp)
1780 1 3.6e-05 : 3404c: movl $0x30,0xffffffcc(%ebp)
1781 17 6.1e-04 : 34053: mov 0xffffff9c(%ebp),%eax
1782 10 3.6e-04 : 34056: mov 0xffffffbc(%ebp),%ecx
1783 13 4.6e-04 : 34059: mov 0x6c(%eax),%edx
1784 6 2.1e-04 : 3405c: cmp 0x14(%edx),%ecx
1785 504 0.0180 : 3405f: jg 342c3 <i965_prepare_composite+0x1433>
1786 6 2.1e-04 : 34065: mov 0x8(%edx),%esi
1787 19 6.8e-04 : 34068: mov 0x10(%edx),%eax
1788 447 0.0160 : 3406b: mov (%edx),%edi
1789 15 5.4e-04 : 3406d: lea (%esi,%eax,1),%edx
1790 1 3.6e-05 : 34070: add $0x4,%eax
1791 14 5.0e-04 : 34073: movl $0x78080003,(%edx)
1792 12 4.3e-04 : 34079: mov 0xffffffc4(%ebp),%ecx
1793 34 0.0012 : 3407c: and %edi,%eax
1794 : 3407e: lea (%esi,%eax,1),%edx
1795 33 0.0012 : 34081: add $0x4,%eax
1796 : 34084: and %edi,%eax
1797 16 5.7e-04 : 34086: mov %ecx,(%edx)
1798 37 0.0013 : 34088: mov 0x2a2c(%ebx),%edx
1799 16 5.7e-04 : 3408e: lea (%esi,%eax,1),%ecx
1800 : 34091: add 0x2a58(%ebx),%edx
1801 42 0.0015 : 34097: add $0x4,%eax
1802 9 3.2e-04 : 3409a: and %edi,%eax
1803 15 5.4e-04 : 3409c: mov %edx,(%ecx)
1804 6 2.1e-04 : 3409e: lea (%esi,%eax,1),%edx
1805 7 2.5e-04 : 340a1: add $0x4,%eax
1806 12 4.3e-04 : 340a4: and %edi,%eax
1807 10 3.6e-04 : 340a6: movl $0x3,(%edx)
1808 19 6.8e-04 : 340ac: lea (%esi,%eax,1),%edx
1809 10 3.6e-04 : 340af: add $0x4,%eax
1810 10 3.6e-04 : 340b2: movl $0x0,(%edx)
1811 16 5.7e-04 : 340b8: mov 0xffffffc8(%ebp),%ecx
1812 55 0.0020 : 340bb: and %edi,%eax
1813 15 5.4e-04 : 340bd: lea (%esi,%eax,1),%edx
1814 15 5.4e-04 : 340c0: add $0x4,%eax
1815 16 5.7e-04 : 340c3: and %edi,%eax
1816 2 7.1e-05 : 340c5: mov %ecx,(%edx)
1817 33 0.0012 : 340c7: lea (%esi,%eax,1),%edx
1818 12 4.3e-04 : 340ca: add $0x4,%eax
1819 8 2.9e-04 : 340cd: and %edi,%eax
1820 4 1.4e-04 : 340cf: mov $0x28,%ecx
1821 12 4.3e-04 : 340d4: movl $0x4850000,(%edx)
1822 14 5.0e-04 : 340da: lea (%esi,%eax,1),%edx
1823 7 2.5e-04 : 340dd: add $0x4,%eax
1824 1 3.6e-05 : 340e0: and %edi,%eax
1825 11 3.9e-04 : 340e2: movl $0x11330004,(%edx)
1826 34 0.0012 : 340e8: lea (%esi,%eax,1),%edx
1827 2 7.1e-05 : 340eb: add $0x4,%eax
1828 : 340ee: and %edi,%eax
1829 9 3.2e-04 : 340f0: movl $0x4850008,(%edx)
1830 22 7.9e-04 : 340f6: lea (%esi,%eax,1),%edx
1831 8 2.9e-04 : 340f9: movl $0x11000008,(%edx)
1832 27 9.6e-04 : 340ff: lea 0x4(%eax),%edx
1833 32 0.0011 : 34102: mov 0x1c(%ebp),%eax
1834 94 0.0034 : 34105: and %edi,%edx
1835 6 2.1e-04 : 34107: test %eax,%eax
1836 : 34109: je 34129 <i965_prepare_composite+0x1299>
1837 14 5.0e-04 : 3410b: lea (%esi,%edx,1),%eax
1838 : 3410e: mov $0x30,%cl
1839 : 34110: movl $0x4850010,(%eax)
1840 12 4.3e-04 : 34116: lea 0x4(%edx),%eax
1841 9 3.2e-04 : 34119: and %edi,%eax
1842 : 3411b: lea (%esi,%eax,1),%edx
1843 2 7.1e-05 : 3411e: movl $0x1100000a,(%edx)
1844 20 7.1e-04 : 34124: lea 0x4(%eax),%edx
1845 9 3.2e-04 : 34127: and %edi,%edx
1846 20 7.1e-04 : 34129: cmp 0xffffffcc(%ebp),%ecx
1847 10 3.6e-04 : 3412c: ja 34416 <i965_prepare_composite+0x1586>
1848 58 0.0021 : 34132: jb 34439 <i965_prepare_composite+0x15a9>
1849 9 3.2e-04 : 34138: mov 0xffffff9c(%ebp),%esi
1850 92 0.0033 : 3413b: mov 0x6c(%esi),%eax
1851 118 0.0042 : 3413e: mov %edx,0x10(%eax)
1852 55 0.0020 : 34141: mov 0x6c(%esi),%eax
1853 22 7.9e-04 : 34144: sub %ecx,0x14(%eax)
1854 249 0.0089 : 34147: test $0x7,%dl
1855 : 3414a: jne 343fa <i965_prepare_composite+0x156a>
1856 8 2.9e-04 : 34150: mov 0xffffff9c(%ebp),%ecx
1857 224 0.0080 : 34153: mov (%ecx),%eax
1858 199 0.0071 : 34155: mov %edx,0x2030(%eax)
1859 16824 0.6004 : 3415b: add $0x8c,%esp
1860 : 34161: mov $0x1,%eax
1862 9 3.2e-04 : 34167: pop %esi
1863 34 0.0012 : 34168: pop %edi
1864 1 3.6e-05 : 34169: pop %ebp
1867 : 3416c: lea 0x0(%esi),%esi
1868 : 34170: andb $0xf8,0x4(%ecx)
1869 1 3.6e-05 : 34174: andw $0xfe3f,0x4(%ecx)
1870 2 7.1e-05 : 3417a: andb $0xc7,0x4(%ecx)
1871 2 7.1e-05 : 3417e: jmp 33a11 <i965_prepare_composite+0xb81>
1872 : 34183: mov (%edx),%eax
1873 5 1.8e-04 : 34185: and $0xfffe3fff,%eax
1874 : 3418a: or $0x40,%ah
1875 : 3418d: mov %eax,(%edx)
1876 : 3418f: movzbl 0x2(%edx),%eax
1877 5 1.8e-04 : 34193: and $0xfffffff1,%eax
1878 : 34196: or $0x2,%eax
1879 : 34199: mov %al,0x2(%edx)
1880 : 3419c: jmp 3368d <i965_prepare_composite+0x7fd>
1881 : 341a1: movl $0x1,0x2a60(%ebx)
1882 : 341ab: jmp 33302 <i965_prepare_composite+0x472>
1883 : 341b0: add $0x1,%edx
1884 : 341b3: jne 3393c <i965_prepare_composite+0xaac>
1885 : 341b9: movl $0x2,0x2a04(%ebx)
1886 : 341c3: movl $0x0,0x2a1c(%ebx)
1887 : 341cd: movl $0x20,0x2a20(%ebx)
1888 : 341d7: movl $0x40,0x2a24(%ebx)
1889 : 341e1: movl $0x400,0x2a40(%ebx)
1890 : 341eb: movl $0x8400,0x2a28(%ebx)
1891 : 341f5: movl $0x8440,0x2a34(%ebx)
1892 : 341ff: movl $0x8580,0x2a38(%ebx)
1893 : 34209: movl $0x89e0,0x2a4c(%ebx)
1894 : 34213: movl $0x8580,0xffffffc0(%ebp)
1895 : 3421a: movl $0x1,0xffffffb8(%ebp)
1896 : 34221: movl $0x0,0xffffffa8(%ebp)
1897 : 34228: movl $0x0,0xffffffac(%ebp)
1898 : 3422f: jmp 3301a <i965_prepare_composite+0x18a>
1899 1 3.6e-05 : 34234: lea 0xffffc274(%ebx),%eax
1900 22 7.9e-04 : 3423a: jmp 33bc0 <i965_prepare_composite+0xd30>
1902 20 7.1e-04 : 34240: mov 0xffffffd0(%ebp),%ecx
1903 62 0.0022 : 34243: lea (%edx,%ecx,1),%eax
1904 2 7.1e-05 : 34246: mov %eax,0x29d4(%ebx)
1905 11 3.9e-04 : 3424c: jmp 331bc <i965_prepare_composite+0x32c>
1906 : 34251: movl $0x0,0x8(%esp)
1907 : 34259: movl $0x8,0x4(%esp)
1908 : 34261: mov 0xffffff98(%ebp),%esi
1909 : 34264: mov %esi,(%esp)
1910 : 34267: call 8358 <I830WaitLpRing@plt>
1911 : 3426c: mov 0xffffff9c(%ebp),%eax
1912 : 3426f: mov 0x6c(%eax),%edx
1913 : 34272: jmp 33cc9 <i965_prepare_composite+0xe39>
1914 : 34277: movl $0x0,0x8(%esp)
1915 : 3427f: movl $0x30,0x4(%esp)
1916 : 34287: mov 0xffffff98(%ebp),%eax
1917 : 3428a: mov %eax,(%esp)
1918 : 3428d: call 8358 <I830WaitLpRing@plt>
1919 : 34292: mov 0x6c(%esi),%edx
1920 : 34295: jmp 33d1d <i965_prepare_composite+0xe8d>
1921 : 3429a: lea 0x0(%esi),%esi
1922 : 342a0: movl $0x0,0x8(%esp)
1923 : 342a8: movl $0x68,0x4(%esp)
1924 : 342b0: mov 0xffffff98(%ebp),%eax
1925 : 342b3: mov %eax,(%esp)
1926 : 342b6: call 8358 <I830WaitLpRing@plt>
1927 : 342bb: mov 0x6c(%esi),%edx
1928 : 342be: jmp 33e05 <i965_prepare_composite+0xf75>
1929 : 342c3: movl $0x0,0x8(%esp)
1930 : 342cb: mov %ecx,0x4(%esp)
1931 : 342cf: mov 0xffffff98(%ebp),%esi
1932 : 342d2: mov %esi,(%esp)
1933 : 342d5: call 8358 <I830WaitLpRing@plt>
1934 : 342da: mov 0xffffff9c(%ebp),%eax
1935 : 342dd: mov 0x6c(%eax),%edx
1936 : 342e0: jmp 34065 <i965_prepare_composite+0x11d5>
1937 27 9.6e-04 : 342e5: mov 0xffffffb8(%ebp),%eax
1938 47 0.0017 : 342e8: test %eax,%eax
1939 : 342ea: je 343e0 <i965_prepare_composite+0x1550>
1940 : 342f0: lea 0xffffc874(%ebx),%eax
1941 17 6.1e-04 : 342f6: mov %eax,0x4(%esp)
1942 4 1.4e-04 : 342fa: mov 0x29f8(%ebx),%eax
1943 1 3.6e-05 : 34300: movl $0x460,0x8(%esp)
1944 27 9.6e-04 : 34308: mov %eax,(%esp)
1945 14 5.0e-04 : 3430b: call 7d88 <memcpy@plt>
1946 20 7.1e-04 : 34310: mov 0x29e8(%ebx),%edi
1947 1 3.6e-05 : 34316: xor %eax,%eax
1948 : 34318: mov $0x8,%ecx
1950 220 0.0079 : 3431e: rep stos %eax,%es:(%edi)
1951 236 0.0084 : 34320: mov 0x29e8(%ebx),%ecx
1952 4 1.4e-04 : 34326: mov 0x2a58(%ebx),%esi
1953 3 1.1e-04 : 3432c: mov (%ecx),%eax
1954 7936 0.2832 : 3432e: mov %esi,%edx
1955 : 34330: add 0x2a38(%ebx),%edx
1956 : 34336: orb $0x80,0x7(%ecx)
1957 4613 0.1646 : 3433a: and $0x3f,%eax
1958 : 3433d: and $0xffffffc0,%edx
1959 : 34340: or %edx,%eax
1960 40 0.0014 : 34342: mov %esi,%edx
1961 5 1.8e-04 : 34344: mov %eax,(%ecx)
1962 : 34346: movzbl (%ecx),%eax
1963 5624 0.2007 : 34349: and $0xfffffff1,%eax
1964 9 3.2e-04 : 3434c: or $0x2,%eax
1965 12 4.3e-04 : 3434f: mov %al,(%ecx)
1966 11 3.9e-04 : 34351: movzwl 0x6(%ecx),%eax
1967 3823 0.1364 : 34355: and $0xfc03,%ax
1968 14 5.0e-04 : 34359: or $0x8,%eax
1969 23 8.2e-04 : 3435c: mov %ax,0x6(%ecx)
1970 16 5.7e-04 : 34360: mov 0x8(%ecx),%eax
1971 752 0.0268 : 34363: add 0x2a40(%ebx),%edx
1972 : 34369: andb $0x81,0xf(%ecx)
1973 2259 0.0806 : 3436d: andb $0x3,0xe(%ecx)
1974 2940 0.1049 : 34371: and $0xfffffc00,%edx
1975 : 34377: and $0x3ff,%eax
1976 4 1.4e-04 : 3437c: or %edx,%eax
1977 : 3437e: mov %eax,0x8(%ecx)
1978 14 5.0e-04 : 34381: mov 0xc(%ecx),%eax
1979 5772 0.2060 : 34384: andb $0xf0,0x8(%ecx)
1980 2356 0.0841 : 34388: and $0xfffe07ff,%eax
1981 : 3438d: or $0x8,%ah
1982 1 3.6e-05 : 34390: mov %eax,0xc(%ecx)
1983 15 5.4e-04 : 34393: jmp 33c5d <i965_prepare_composite+0xdcd>
1984 15 5.4e-04 : 34398: movl $0x28,0xffffffbc(%ebp)
1985 3 1.1e-04 : 3439f: movl $0x10,0xffffffc4(%ebp)
1986 : 343a6: movl $0x78090003,0xffffffc8(%ebp)
1987 : 343ad: movl $0x28,0xffffffcc(%ebp)
1988 17 6.1e-04 : 343b4: jmp 34053 <i965_prepare_composite+0x11c3>
1989 : 343b9: sub $0x1,%edx
1990 : 343bc: jne 3393c <i965_prepare_composite+0xaac>
1991 : 343c2: jmp 341b9 <i965_prepare_composite+0x1329>
1992 7 2.5e-04 : 343c7: lea 0xffffbc74(%ebx),%eax
1993 33 0.0012 : 343cd: lea 0x0(%esi),%esi
1994 8 2.9e-04 : 343d0: jmp 33bc0 <i965_prepare_composite+0xd30>
1995 17 6.1e-04 : 343d5: lea 0xffffb554(%ebx),%eax
1996 43 0.0015 : 343db: jmp 33a76 <i965_prepare_composite+0xbe6>
1997 10 3.6e-04 : 343e0: lea 0xffffccd4(%ebx),%eax
1998 : 343e6: jmp 342f6 <i965_prepare_composite+0x1466>
1999 : 343eb: movl $0x2,0x2a64(%ebx)
2000 : 343f5: jmp 33316 <i965_prepare_composite+0x486>
2001 : 343fa: lea 0xffffd134(%ebx),%eax
2002 : 34400: mov %eax,0x4(%esp)
2003 : 34404: lea 0xffff553c(%ebx),%eax
2004 : 3440a: mov %edx,0x8(%esp)
2005 : 3440e: mov %eax,(%esp)
2006 : 34411: call 8a18 <FatalError@plt>
2007 : 34416: mov 0xffffffbc(%ebp),%esi
2008 : 34419: lea 0xffffd134(%ebx),%eax
2009 : 3441f: mov %eax,0x4(%esp)
2010 : 34423: lea 0xffffabdc(%ebx),%eax
2011 : 34429: mov %ecx,0x8(%esp)
2012 : 3442d: mov %eax,(%esp)
2013 : 34430: mov %esi,0xc(%esp)
2014 : 34434: call 8a18 <FatalError@plt>
2015 : 34439: mov 0xffffffbc(%ebp),%eax
2016 : 3443c: mov %ecx,0x8(%esp)
2017 : 34440: mov %eax,0xc(%esp)
2018 : 34444: lea 0xffffd134(%ebx),%eax
2019 : 3444a: mov %eax,0x4(%esp)
2020 : 3444e: lea 0xffff5508(%ebx),%eax
2021 : 34454: mov %eax,(%esp)
2022 : 34457: call 8a18 <FatalError@plt>
2027 :Disassembly of section .fini:
2029 :/home/cworth/opt/xorg/lib/xorg/modules/drivers/intel_drv.so: file format elf32-i386
2031 :Disassembly of section .init:
2032 :Disassembly of section .plt:
2033 :Disassembly of section .text:
2035 00011330 <I830WaitLpRing>: /* I830WaitLpRing total: 94669 3.3786 */
projects / cworth.org / blob